公开(公告)号：US20190113568A1

公开(公告)日：2019-04-18

申请号：US15785792

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Dereck Fernandes ,  Manivannan Balu ,  Yong Yuenyongsgool ,  Timothy Phoenix ,  Steve Bradley

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31724 ,  G01R31/31723 ,  G01R31/3177 ,  G11C29/14 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

公开(公告)号：US12259705B2

公开(公告)日：2025-03-25

申请号：US17530633

申请日：2021-11-19

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Manivannan Balu ,  Timothy Phoenix ,  Sankar Rangarajan

IPC: G05B19/406

Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

公开(公告)号：US20190340047A1

公开(公告)日：2019-11-07

申请号：US15970159

申请日：2018-05-03

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Manivannan Balu

IPC: G06F11/07 ,  G06F13/40

Abstract: A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.

公开(公告)号：US20220187788A1

公开(公告)日：2022-06-16

申请号：US17530633

申请日：2021-11-19

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Manivannan Balu ,  Timothy Phoenix ,  Sankar Rangarajan

IPC: G05B19/406

Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

公开(公告)号：US10860408B2

公开(公告)日：2020-12-08

申请号：US15970159

申请日：2018-05-03

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Manivannan Balu

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/40

Abstract: A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.

公开(公告)号：US10352998B2

公开(公告)日：2019-07-16

申请号：US15785792

申请日：2017-10-17

Applicant: Microchip Technology Incorporated

Inventor： Stephen Bowling ,  Igor Wojewoda ,  Dereck Fernandes ,  Manivannan Balu ,  Yong Yuenyongsgool ,  Timothy Phoenix ,  Steve Bradley

IPC: G01R31/317 ,  G01R31/3177 ,  G06F15/80 ,  G11C29/14 ,  G11C29/26 ,  G11C29/48 ,  G11C29/04

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.