公开(公告)号：US20230176898A1

公开(公告)日：2023-06-08

申请号：US18073075

申请日：2022-12-01

Applicant: Microchip Technology Incorporated

Inventor： Michael Catherwood ,  Howard Schlunder ,  David Mickey

IPC: G06F9/48 ,  G06F8/71

CPC classification number: G06F9/4831 ,  G06F8/71

Abstract: A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.