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    Run Time ECC Error Injection Scheme for Hardware Validation
    1.
    发明申请
    Run Time ECC Error Injection Scheme for Hardware Validation 审中-公开
    硬件验证的运行时ECC错误注入方案

    公开(公告)号：US20160292059A1

    公开(公告)日：2016-10-06

    申请号：US15089352

    申请日：2016-04-01

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  Brant Ivey ,  Sankar Rangarajan

    IPC: G06F11/263 ,  G06F11/10 ,  G06F11/22

    CPC classification number: G06F11/263 ,  G06F11/10 ,  G06F11/2205 ,  G06F11/2215

    Abstract: Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.

    Abstract translation: 公开了用于硬件验证的运行时纠错码（“ECC”）错误注入方案的系统和方法。 系统和方法包括配置读取路径以内部转发读取数据，以及经由读取故障注入逻辑将至少一个故障位注入转发的读取数据。 系统和方法还可以包括配置写入路径以内部转发写入数据，以及经由写入故障注入逻辑将至少一个故障位注入转发的写入数据。

    Accelerated Read, Modify, Write Operations
    2.
    发明公开
    Accelerated Read, Modify, Write Operations 审中-公开

    公开(公告)号：US20230176738A1

    公开(公告)日：2023-06-08

    申请号：US17990013

    申请日：2022-11-18

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

    Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.

    Central Processing Unit With DSP Engine And Enhanced Context Switch Capabilities
    5.
    发明申请
    Central Processing Unit With DSP Engine And Enhanced Context Switch Capabilities 审中-公开
    具有DSP引擎和增强型上下文切换功能的中央处理单元

    公开(公告)号：US20160321075A1

    公开(公告)日：2016-11-03

    申请号：US15141817

    申请日：2016-04-28

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F9/30

    Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.

    Abstract translation: 集成电路装置具有包括数字信号处理（DSP）引擎和多个上下文的第一中央处理单元，每个上下文具有具有多个寄存器和DSP上下文的CPU上下文，其中DSP上下文具有控制位和 多个DSP寄存器，其中在集成电路器件复位之后，将所有DSP上下文的控制位链接在一起，使得写入DSP上下文的控制位的数据被写入所有其它DSP上下文的相应控制位，并且仅 在上下文切换到另一个上下文并修改另一个DSP上下文中的至少一个控制位之后，另一个上下文的控制位从链路中被切断，以形成DSP上下文的独立控制位。

    MULTIBIT SHIFT INSTRUCTION
    6.
    发明公开
    MULTIBIT SHIFT INSTRUCTION 审中-公开

    公开(公告)号：US20230176866A1

    公开(公告)日：2023-06-08

    申请号：US17982980

    申请日：2022-11-08

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

    IPC: G06F9/30

    CPC classification number: G06F9/30032 ,  G06F9/30123

    Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

    Configurable mailbox data buffer apparatus
    8.
    发明授权
    Configurable mailbox data buffer apparatus 有权

    公开(公告)号：US10120815B2

    公开(公告)日：2018-11-06

    申请号：US15184789

    申请日：2016-06-16

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris

    IPC: G06F3/00 ,  G06F13/10 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42 ,  G06F15/167

    Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

    Vector fetch bus error handling
    9.
    发明授权
    Vector fetch bus error handling 有权

    公开(公告)号：US12001270B2

    公开(公告)日：2024-06-04

    申请号：US18075458

    申请日：2022-12-06

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F11/00 ,  G06F9/30 ,  G06F11/07

    CPC classification number: G06F11/0745 ,  G06F9/30101

    Abstract: A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

    VECTOR FETCH BUS ERROR HANDLING
    10.
    发明公开
    VECTOR FETCH BUS ERROR HANDLING 审中-公开

    公开(公告)号：US20230176937A1

    公开(公告)日：2023-06-08

    申请号：US18075458

    申请日：2022-12-06

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F11/07 ,  G06F9/30

    CPC classification number: G06F11/0745 ,  G06F9/30101

    Abstract: A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

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