公开(公告)号：US09972578B2

公开(公告)日：2018-05-15

申请号：US15471889

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Lee Furey ,  Rohan Raghunathan

IPC: H01L23/00 ,  H01L23/552 ,  H01L25/065 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/552 ,  H01L23/3171 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.

公开(公告)号：US20170287850A1

公开(公告)日：2017-10-05

申请号：US15471889

申请日：2017-03-28

Applicant: Microchip Technology Incorporated

Inventor： Gregory Dix ,  Lee Furey ,  Rohan Raghunathan

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/3171 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.