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公开(公告)号:US20140284812A1
公开(公告)日:2014-09-25
申请号:US14302160
申请日:2014-06-11
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L23/528
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成,随后可以与第一组横向的第二组平行条纹掩模形成。 例如,可以使用一组掩模来蚀刻介电层,以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后,该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。
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公开(公告)号:US20180151415A1
公开(公告)日:2018-05-31
申请号:US15881539
申请日:2018-01-26
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L27/105
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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公开(公告)号:US09899254B2
公开(公告)日:2018-02-20
申请号:US15471420
申请日:2017-03-28
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L27/105
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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公开(公告)号:US11056383B2
公开(公告)日:2021-07-06
申请号:US15881539
申请日:2018-01-26
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L27/115 , H01L27/105 , H01L23/522 , H01L23/528 , H01L21/768 , H01L27/11521
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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公开(公告)号:US20140048956A1
公开(公告)日:2014-02-20
申请号:US14066340
申请日:2013-10-29
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L23/522 , H01L23/528
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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公开(公告)号:US20170200635A1
公开(公告)日:2017-07-13
申请号:US15471420
申请日:2017-03-28
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L27/105
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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公开(公告)号:US09627251B2
公开(公告)日:2017-04-18
申请号:US14722889
申请日:2015-05-27
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L27/105 , H01L23/522 , H01L23/528 , H01L27/11521
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
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公开(公告)号:US09059261B2
公开(公告)日:2015-06-16
申请号:US14302160
申请日:2014-06-11
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L27/105 , H01L23/522 , H01L23/528 , H01L27/115
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成,随后可以与第一组横向的第二组平行条纹掩模形成。 例如,可以使用一组掩模来蚀刻介电层,以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后,该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。
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公开(公告)号:US20150262867A1
公开(公告)日:2015-09-17
申请号:US14722889
申请日:2015-05-27
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: H01L21/768 , H01L27/105
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成,随后可以与第一组横向的第二组平行条纹掩模形成。 例如,可以使用一组掩模来蚀刻介电层,以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后,该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。
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公开(公告)号:US08759980B2
公开(公告)日:2014-06-24
申请号:US14066340
申请日:2013-10-29
Applicant: Micron Technology, Inc.
Inventor: Roberto Somaschini , Alessandro Vaccaro , Paolo Tessariol , Giulio Albini
IPC: G11C11/24
CPC classification number: H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L27/1052 , H01L27/11521 , H01L2924/0002 , H01L2924/00
Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成,随后可以与第一组横向的第二组平行条纹掩模形成。 例如,可以使用一组掩模来蚀刻介电层,以形成平行间隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后,该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。
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