公开(公告)号：US09378157B2

公开(公告)日：2016-06-28

申请号：US14324915

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Marco Messina ,  Antonino Capri' ,  Salvatore Giove ,  Antonino La Spina ,  Vijay Malhi

IPC: G06F21/00 ,  G06F12/14 ,  G06F21/10 ,  G06F21/34

CPC classification number: G06F12/1466 ,  G06F12/1433 ,  G06F12/1458 ,  G06F21/10 ,  G06F21/34

Abstract: Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括允许外部设备访问存储器件的装置和方法。 一种方法包括在存储装置处接收来自外部设备的访问存储设备的存储区域并执行存储区域的解锁过程的请求。 解锁过程包括将第一代码从存储器设备发送到外部设备，以及从外部设备在存储器设备处接收第二代码。 第二代码将由对第一代码执行的第一加密处理生成以获得第二代码。 基于所接收的第二代码与第一代码具有预定关系的确定，临时解锁存储区域以允许外部设备访问存储区域。 描述附加的装置和方法。

公开(公告)号：US20220197552A1

公开(公告)日：2022-06-23

申请号：US17125888

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Simone Corbetta ,  Antonino Capri' ,  Alessandro Lucio Iannuzzi ,  Filippo Leonini

IPC: G06F3/06

Abstract: Various embodiments provide a memory system architecture for heterogeneous memory technologies, which can be implemented by a memory sub-system. A memory system architecture of some embodiments can support servicing an individual command request using different (heterogeneous) memory technologies, such as different types of memory devices (e.g., heterogeneous memory devices), different types of memory device controllers (e.g., heterogeneous memory device controllers), different types of data paths (e.g., data paths with different protocols or protocol constrains), or some combination thereof. According to various embodiments, the memory system architecture uses tracking and management of multiple command responses to service a single command request from a host system.

公开(公告)号：US20250077348A1

公开(公告)日：2025-03-06

申请号：US18776730

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Antonino Capri' ,  Daniele Balluchi ,  Joseph M. McCrate ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F11/10

Abstract: A variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. The one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. Arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. Other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. Combinations of arrangements may be implemented. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11614892B2

公开(公告)日：2023-03-28

申请号：US17125888

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Simone Corbetta ,  Antonino Capri' ,  Alessandro Lucio Iannuzzi ,  Filippo Leonini

IPC: G06F3/06

Abstract: Various embodiments provide a memory system architecture for heterogeneous memory technologies, which can be implemented by a memory sub-system. A memory system architecture of some embodiments can support servicing an individual command request using different (heterogeneous) memory technologies, such as different types of memory devices (e.g., heterogeneous memory devices), different types of memory device controllers (e.g., heterogeneous memory device controllers), different types of data paths (e.g., data paths with different protocols or protocol constrains), or some combination thereof. According to various embodiments, the memory system architecture uses tracking and management of multiple command responses to service a single command request from a host system.

公开(公告)号：US20140325176A1

公开(公告)日：2014-10-30

申请号：US14324915

申请日：2014-07-07

Applicant: Micron Technology, Inc.

Inventor： Marco Messina ,  Antonino Capri' ,  Salvatore Giove ,  Antonino La Spina ,  Vijay Malhi

IPC: G06F12/14

CPC classification number: G06F12/1466 ,  G06F12/1433 ,  G06F12/1458 ,  G06F21/10 ,  G06F21/34

Abstract: Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括允许外部设备访问存储器件的装置和方法。 一种方法包括在存储装置处接收来自外部设备的访问存储设备的存储区域并执行存储区域的解锁过程的请求。 解锁过程包括将第一代码从存储器设备发送到外部设备，以及从外部设备在存储器设备处接收第二代码。 第二代码将由对第一代码执行的第一加密处理生成以获得第二代码。 基于所接收的第二代码与第一代码具有预定关系的确定，临时解锁存储区域以允许外部设备访问存储区域。 描述附加的装置和方法。