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公开(公告)号：US20220069207A1
公开(公告)日：2022-03-03
申请号：US17007156
申请日：2020-08-31
摘要： The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.
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公开(公告)号：US12072766B2
公开(公告)日：2024-08-27
申请号：US17959412
申请日：2022-10-04
发明人： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC分类号： G06F11/10
CPC分类号： G06F11/1096
摘要： A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
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公开(公告)号：US20240303159A1
公开(公告)日：2024-09-12
申请号：US18444523
申请日：2024-02-16
发明人： Joseph M. McCrate , Marco Sforzin , Paolo Amato , Brian M. Twait
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1004 , G06F11/1016
摘要： A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that can correct residual bit errors. The bit errors correctable by the ECC schemes not only include those errors that have been existing in input data used for the RAID process, but also those bit errors may have been propagated due to the existing errors.
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公开(公告)号：US20210005254A1
公开(公告)日：2021-01-07
申请号：US16460863
申请日：2019-07-02
摘要： Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.
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公开(公告)号：US20240111629A1
公开(公告)日：2024-04-04
申请号：US17959412
申请日：2022-10-04
发明人： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC分类号： G06F11/10
CPC分类号： G06F11/1096
摘要： A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
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公开(公告)号：US20240004756A1
公开(公告)日：2024-01-04
申请号：US18211881
申请日：2023-06-20
CPC分类号： G06F11/1068 , G06F11/0772
摘要： Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.
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公开(公告)号：US11711987B2
公开(公告)日：2023-07-25
申请号：US17007156
申请日：2020-08-31
CPC分类号： H10N70/8265 , H10B63/00 , H10N70/063 , H10N70/841 , H10N70/8833
摘要： The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.
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公开(公告)号：US20230014459A1
公开(公告)日：2023-01-19
申请号：US17953247
申请日：2022-09-26
摘要： The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
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公开(公告)号：US11455210B1
公开(公告)日：2022-09-27
申请号：US17239864
申请日：2021-04-26
摘要： The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
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公开(公告)号：US11962327B2
公开(公告)日：2024-04-16
申请号：US17896957
申请日：2022-08-26
CPC分类号： H03M13/154 , H03M13/1575 , H03M13/153 , H03M13/1545 , H03M13/373 , H03M13/3746
摘要： Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.
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