公开(公告)号：US10991416B1

公开(公告)日：2021-04-27

申请号：US16803486

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Brian J. Ladner ,  Daniel B. Penney

IPC: G06F13/28 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/4093 ,  H03K19/20

Abstract: Systems and methods may involve circuitry that receives a first transition of a clocking signal. The circuitry may also to enable a compensation circuit characterized by a capacitance in response to the first transition of the clocking signal and may receive subsequent transitions of the clocking signal. The circuitry may also apply the capacitance to the subsequent transitions of the clocking signal after enabling the compensation circuit to generate a compensated clocking signal characterized by an adjusted duty cycle relative to a duty cycle of the clocking signal.

公开(公告)号：US11315622B2

公开(公告)日：2022-04-26

申请号：US16834144

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Parthasarathy Gajapathy ,  Brian J. Ladner

IPC: G11C11/4076 ,  H03K3/037 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4093

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

公开(公告)号：US20210304808A1

公开(公告)日：2021-09-30

申请号：US16834144

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Parthasarathy Gajapathy ,  Brian J. Ladner

IPC: G11C11/4076 ,  G11C11/4091 ,  H03K3/037

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.