公开(公告)号：US11488645B2

公开(公告)日：2022-11-01

申请号：US15965263

申请日：2018-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Parthasarathy Gajapathy

IPC: G11C7/00 ,  G11C7/12 ,  G11C8/18 ,  G11C7/10 ,  G11C11/4076

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

公开(公告)号：US10163486B1

公开(公告)日：2018-12-25

申请号：US15693194

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy

IPC: G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C8/16

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

公开(公告)号：US09135984B2

公开(公告)日：2015-09-15

申请号：US14133272

申请日：2013-12-18

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy ,  David R. Brown

IPC: G11C7/00 ,  G11C11/4093 ,  G11C7/10

CPC classification number: G11C11/4093 ,  G11C7/1009

Abstract: Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. The multiplexer may change the order of the data words to group masked data words together and to group unmasked data words together. The multiplexer may also change the order of the data mask to group masking bits together and to group unmasking bits together. The apparatus may use the data words with the changed order and the data mask with the changed order to write data to the memory array.

Abstract translation: 公开了将数据写入缓冲器的存储器阵列的装置和方法。 一种这样的装置可以包括接收数据字和数据掩码的多路复用器。 复用器可以将数据字的顺序改变为将屏蔽的数据字组合在一起，并将未屏蔽的数据字组合在一起。 多路复用器还可以将数据掩码的顺序改变为组屏蔽位在一起，并且将未屏蔽位组合在一起。 设备可以使用具有改变顺序的数据字和具有改变顺序的数据掩码将数据写入存储器阵列。

公开(公告)号：US20230039948A1

公开(公告)日：2023-02-09

申请号：US17966350

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy

IPC: G11C7/12 ,  G11C8/18 ,  G11C7/10 ,  G11C11/4076

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

公开(公告)号：US20190101975A1

公开(公告)日：2019-04-04

申请号：US16205356

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G06F3/00 ,  G11C7/10 ,  G11C11/4063 ,  G06F13/16

CPC classification number: G06F3/002 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/109 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4076 ,  G11C2207/2272

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

公开(公告)号：US20190066758A1

公开(公告)日：2019-02-28

申请号：US16039995

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy

IPC: G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/1093 ,  G11C8/06 ,  G11C8/16 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4093

Abstract: A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal.

公开(公告)号：US20220383930A1

公开(公告)日：2022-12-01

申请号：US17333203

申请日：2021-05-28

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy ,  Kallol Mazumder

IPC: G11C11/4076 ,  G11C11/4093 ,  G06F1/3296 ,  G06F1/3234

Abstract: Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.

公开(公告)号：US11315622B2

公开(公告)日：2022-04-26

申请号：US16834144

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Parthasarathy Gajapathy ,  Brian J. Ladner

IPC: G11C11/4076 ,  H03K3/037 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4093

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

公开(公告)号：US20210304808A1

公开(公告)日：2021-09-30

申请号：US16834144

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Parthasarathy Gajapathy ,  Brian J. Ladner

IPC: G11C11/4076 ,  G11C11/4091 ,  H03K3/037

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

公开(公告)号：US20200081520A1

公开(公告)日：2020-03-12

申请号：US16684183

申请日：2019-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G06F3/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

Abstract: The systems and methods provided herein relate to a command interface/memory device that supports multiple modes of command acquisition. A current command acquisition mode from a set of supported command acquisition modes that each define a corresponding command execution frequency is identified. Based upon the identified mode, clock cycles that will be used to acquire portions of a command address from are identified. The portions of the command address are acquired from the identified clock cycles and a command based upon the acquired portions of the command address is executed.