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公开(公告)号：US11922011B2
公开(公告)日：2024-03-05
申请号：US17464442
申请日：2021-09-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Johnny A. Lam , Samyukta Mudugal , Sanjay Subbarao , Byron D. Harris , Daniel A. Boals
IPC: G06F3/06
CPC classification number: G06F3/0604 , G06F3/0655 , G06F3/0679
Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address. The mapping is updated to associate the set of virtual MUs with the second physical address.
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公开(公告)号：US20240012751A1
公开(公告)日：2024-01-11
申请号：US17811796
申请日：2022-07-11
Applicant: Micron Technology, Inc.
Inventor： John J. Kane , Byron D. Harris , Vivek Shivhare
CPC classification number: G06F12/0238 , G06F3/0616 , G06F3/0655 , G06F3/0679 , G06F2212/7211
Abstract: Methods, systems, and devices for adaptive wear leveling for a memory system are described. A memory system may implement an adaptive rate for performing various wear leveling operations, such as an adaptive rate for performing wear leveling evaluations, or an adaptive rate for performing wear leveling data transfers, among other examples. For example, a memory system may begin with or default to performing wear leveling operations in accordance with a relatively slower rate, and adjust (e.g., accelerate) wear leveling operations based on detecting a relatively greater demand to perform wear leveling operations. In some such examples, wear leveling operations may be capped at a rate (e.g., a maximum rate), which may limit a degradation of memory system performance while performing wear leveling operations. As wear distribution improves, the memory system may adjust (e.g., decelerate) wear leveling operations.
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公开(公告)号：US20230061180A1
公开(公告)日：2023-03-02
申请号：US17464442
申请日：2021-09-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Johnny A. Lam , Samyukta Mudugal , Sanjay Subbarao , Byron D. Harris , Daniel A. Boals
IPC: G06F3/06
Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address. The mapping is updated to associate the set of virtual MUs with the second physical address.
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公开(公告)号：US20200133849A1
公开(公告)日：2020-04-30
申请号：US16175559
申请日：2018-10-30
Applicant: Micron Technology, Inc.
Inventor： Byron D. Harris , Karl D. Schuh
Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.
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公开(公告)号：US12260101B2
公开(公告)日：2025-03-25
申请号：US18374982
申请日：2023-09-29
Applicant: Micron Technology, Inc.
Inventor： Tom V. Geukens , Byron D. Harris
IPC: G06F3/06
Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
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Patent Agency Ranking
公开(公告)号：US20240302991A1
公开(公告)日：2024-09-12
申请号：US18651452
申请日：2024-04-30
Applicant: Micron Technology, Inc.
Inventor： John J. Kane , Byron D. Harris , Vivek Shivhare
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.
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公开(公告)号：US20240231660A9
公开(公告)日：2024-07-11
申请号：US18374982
申请日：2023-09-29
Applicant: Micron Technology, Inc.
Inventor： Tom V. Geukens , Byron D. Harris
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0652 , G06F3/0659 , G06F3/0679
Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
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公开(公告)号：US11030089B2
公开(公告)日：2021-06-08
申请号：US16146955
申请日：2018-09-28
Applicant: Micron Technology, Inc.
Inventor： Daniel A. Boals , Byron D. Harris , Karl D. Schuh , Amy L. Wohlschlegel
Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.
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公开(公告)号：US10860243B2
公开(公告)日：2020-12-08
申请号：US16205999
申请日：2018-11-30
Applicant: Micron Technology, Inc.
Inventor： Daniel A. Boals , Karl D. Schuh , Byron D. Harris
Abstract: Each of a multiple cursors is assigned a respective generator of multiple generators. The cursors are used to perform an operation on a set of logical unit numbers (LUN) associated with memory devices. Multiple sequences of LUNs are identified based on the generators. Each of the cursors is associated with one of the sequences of LUNs. The operation on the set of LUNs associated with the memory devices is performed using the sequences of LUNs. The operation on the set of LUNs is performed in an order provided by the sequences of LUNs to reduce a probability of collision by the cursors in the performance of the operation.
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公开(公告)号：US12066914B2
公开(公告)日：2024-08-20
申请号：US17464023
申请日：2021-09-01
Applicant: Micron Technology, Inc.
Inventor： Andrei Konan , Byron D. Harris
IPC: G06F11/30 , G06F9/4401 , G06F11/32
CPC classification number: G06F11/3037 , G06F9/4403 , G06F11/3024 , G06F11/3075 , G06F11/328
Abstract: Systems and methods are disclosed for enabling a memory sub-system to perform firmware-based monitoring of system state information without adding latency to the memory sub-system. The memory sub-system controller can include multiple CPUs which can be employed to perform different tasks. The memory sub-system controller can employ one of the frontend CPUs as a monitoring CPU capable of executing a data-gathering task to retrieve system state information from another CPU.
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