SELF-CALIBRATION IN A MEMORY DEVICE

    公开(公告)号:US20240420790A1

    公开(公告)日:2024-12-19

    申请号:US18635869

    申请日:2024-04-15

    Abstract: Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.

    SELF-CALIBRATION IN A MEMORY DEVICE

    公开(公告)号:US20240420789A1

    公开(公告)日:2024-12-19

    申请号:US18638379

    申请日:2024-04-17

    Abstract: Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.

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