公开(公告)号：US20240429905A1

公开(公告)日：2024-12-26

申请号：US18591581

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Chulkyu Lee

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/0944

Abstract: A device includes a signal path including a plurality of inverters connected in series, which comprises a first inverter having a first input and a having first output, a second inverter having a second input coupled to the first output of the first inverter and having a second output, and a third inverter having a third input coupled to the second output of the second inverter and having a third output. The device also includes a first feedback path connecting the second output of the second inverter to the first input of the first inverter, the first feedback path including a fourth inverter and a second feedback path connecting the third output of the third inverter to the second input of the second inverter, the second feedback path including a fifth inverter.

公开(公告)号：US20250165340A1

公开(公告)日：2025-05-22

申请号：US18901895

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Timothy M. Hollis ,  Eric J. Stave ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G06F11/10

Abstract: A decision counter circuit is used in a self-adaptation circuit to apply digital averaging to input signals to obtain adaptive settings of circuit parameters for a memory chip of a memory device during the operation. Individual adaptive settings of the parameters (e.g., impedance, capacitance, equalization parameters) during operation are obtained for each of the memory chips in the memory device. The self-adaptation enables equalization adjustment across temperature and voltage drift.

公开(公告)号：US20240420789A1

公开(公告)日：2024-12-19

申请号：US18638379

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G11C29/12 ,  G11C29/20

Abstract: Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.

公开(公告)号：US20240305507A1

公开(公告)日：2024-09-12

申请号：US18584986

申请日：2024-02-22

Applicant: Micron Technology, Inc.

Inventor： Chulkyu Lee ,  Timothy M. Hollis

IPC: H04L25/03 ,  G06F13/16

CPC classification number: H04L25/03267 ,  G06F13/1668 ,  H04L25/03057

Abstract: Methods, apparatuses, and systems related to an apparatus for managing on-die inter-symbol interference (ISI) are described. The apparatus may include (1) a single communication path with a set of drivers and (2) an on-die ISI prevention circuit coupled to the communication path in parallel. The single communication path may be used to propagate a slower speed signal and a higher speed signal. The on-die ISI prevention circuit may be configured to adjust the propagated signal for one of the speeds to reduce the ISI in the communicated signal.

公开(公告)号：US20240420790A1

公开(公告)日：2024-12-19

申请号：US18635869

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G11C29/42 ,  G11C29/12

Abstract: Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.