COMPONENT INTER-DIGITATED VIAS AND LEADS

    公开(公告)号:US20250125266A1

    公开(公告)日:2025-04-17

    申请号:US18990461

    申请日:2024-12-20

    Abstract: Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).

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