公开(公告)号：US20180089469A1

公开(公告)日：2018-03-29

申请号：US15829718

申请日：2017-12-01

Applicant: Micron Technology, Inc.

Inventor： Kenny T. Coker ,  David A. Pohm ,  Stephen P. Van Aken ,  Michael B. Danielson

IPC: G06F21/78 ,  G06F21/60

CPC classification number: G06F21/78 ,  G06F21/60 ,  G06F21/602 ,  G06F21/72 ,  G06F21/76

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

公开(公告)号：US09864879B2

公开(公告)日：2018-01-09

申请号：US14876600

申请日：2015-10-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenny T. Coker ,  David A. Pohm ,  Stephen P. Van Aken ,  Michael B. Danielson

IPC: H04L29/06 ,  G06F21/78 ,  G06F21/60

CPC classification number: G06F21/78 ,  G06F21/60 ,  G06F21/602 ,  G06F21/72 ,  G06F21/76

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

公开(公告)号：US20180357449A1

公开(公告)日：2018-12-13

申请号：US16105640

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Kenny T. Coker ,  David A. Pohm ,  Stephen P. Van Aken ,  Michael B. Danielson

IPC: G06F21/78 ,  G06F21/76 ,  G06F21/72 ,  G06F21/60

CPC classification number: G06F21/78 ,  G06F21/60 ,  G06F21/602 ,  G06F21/72 ,  G06F21/76

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations, An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

公开(公告)号：US10068109B2

公开(公告)日：2018-09-04

申请号：US15829718

申请日：2017-12-01

Applicant: Micron Technology, Inc.

Inventor： Kenny T. Coker ,  David A. Pohm ,  Stephen P. Van Aken ,  Michael B. Danielson

IPC: H04L29/06 ,  G06F21/78 ,  G06F21/60

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.