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1.发明授权公开(公告)号：US11804856B2
公开(公告)日：2023-10-31
申请号：US17699131
申请日：2022-03-20
Applicant: Micron Technology, Inc.
Inventor： Robert B. Eisenhuth , Stephen P. Van Aken
CPC classification number: H03M13/256 , G06F3/0619 , G06F3/0655 , G06F3/0679 , G06F11/1068 , H03M13/1515
Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.
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公开(公告)号：US20160364293A1
公开(公告)日：2016-12-15
申请号：US15246957
申请日：2016-08-25
Applicant: Micron Technology, Inc.
Inventor： Stephen P. Van Aken
CPC classification number: G06F11/1068 , G06F11/1076 , G11C29/52 , H03M13/15 , H03M13/151 , H03M13/1515 , H03M13/152 , H03M13/157 , H03M13/159 , H03M13/1595 , H04L1/0057
Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.
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3.发明申请ADVANCED BITWISE OPERATIONS AND APPARATUS IN A MULTI-LEVEL SYSTEM WITH NONVOLATILE MEMORY 审中-公开具有非易失性存储器的多级系统中的先进的比特运算和设备公开(公告)号：US20160314039A1
公开(公告)日：2016-10-27
申请号：US15202123
申请日：2016-07-05
Applicant: Micron Technology, Inc.
Inventor： Robert B. Eisenhuth , Stephen P. Van Aken
CPC classification number: G06F11/1012 , G06F11/10 , H03M13/1515 , H03M13/152 , H03M13/256 , H03M13/353 , H03M13/356 , H03M13/6362
Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.
Abstract translation: 数字系统，组件和方法被配置有非易失性存储器，用于使用码字存储数字数据。 数据存储在存储器中，每个存储器的每个存储单元使用多个位。 基于输入参数，可以在代码字到码字的基础上改变与存储器有关的写入操作和读取操作的代码效率。 代码效率可以根据改变任何一个输入参数而改变，包括由存储器存储的位密度。 描述存储和读取分数位密度。
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公开(公告)号：US09374343B2
公开(公告)日：2016-06-21
申请号：US14096436
申请日：2013-12-04
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Stephen P. Van Aken , Gerald L. Cadloni , John L. Seabury , Robert B. Eisenhuth
CPC classification number: H04L1/0041 , G06F11/1072 , H03M13/253 , H03M13/2936 , H03M13/353 , H04L63/0428
Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
Abstract translation: 系统使用多级编码，其中多个符号的每个符号表示用于使用多级传输信道传送的用户数据符号流中的多于一位的信息。 以数字逐位形式表示用户数据符号，使得每个符号被呈现为多个位，并且每个位受到不同的误差概率。 基于与多个中的每个位相关联的不同误差概率应用纠错过程。 通道可被配置为支持马赛克瓦片结构，每个瓦片包含通道符号，使得所选择的瓦片具有与其他瓦片不同的集体误差概率。 可以将定制编码应用于瓦片结构，以基于总体可用校正功率将所选量的误差校正功率分配给所选择的瓦片。
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公开(公告)号：US20180357449A1
公开(公告)日：2018-12-13
申请号：US16105640
申请日：2018-08-20
Applicant: Micron Technology, Inc.
Inventor： Kenny T. Coker , David A. Pohm , Stephen P. Van Aken , Michael B. Danielson
CPC classification number: G06F21/78 , G06F21/60 , G06F21/602 , G06F21/72 , G06F21/76
Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations, An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.
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Patent Agency Ranking
6.发明授权Control arrangements and methods for accessing block oriented nonvolatile memory 有权用于访问面向块的非易失性存储器的控制布置和方法公开(公告)号：US09069661B2
公开(公告)日：2015-06-30
申请号：US14092731
申请日：2013-11-27
Applicant: Micron Technology, Inc.
Inventor： Stephen P. Van Aken
CPC classification number: G06F12/0246 , G06F2212/1028 , G06F2212/7201 , G06F2212/7205 , G06F2212/7206 , G06F2212/7207 , G06F2212/7211 , Y02D10/13
Abstract: A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes a plurality of modules, each module including a nonvolatile memory section. In one feature, at least a particular one of the modules is configured to independently maintain a module portion of a distributed flash translation layer for the nonvolatile memory section of only that particular module based on one or more module input parameters. In another feature, a particular module defines an independent execution of at least one of a wear leveling function, a garbage collection function and a bit density function. Associated methods are described.
Abstract translation: 存储器系统与主机设备数字通信，以提供主机设备的数据存储容量。 存储器系统包括多个模块，每个模块包括非易失性存储器部分。 在一个特征中，模块中的至少一个特定模块被配置为基于一个或多个模块输入参数独立地维护仅该特定模块的非易失性存储器部分的分布式闪存转换层的模块部分。 在另一个特征中，特定模块定义了磨损均衡功能，垃圾收集功能和位密度函数中的至少一个的独立执行。 描述相关方法。
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公开(公告)号：US08862969B2
公开(公告)日：2014-10-14
申请号：US13931519
申请日：2013-06-28
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Gerald L. Cadloni , Larry J. Koudele , John L. Seabury , Stephen P. Van Aken , Guy R. Wagner
CPC classification number: G06F11/1076 , G06F11/08 , G06F11/1048 , G11C7/1006 , G11C11/5621 , G11C11/5642 , G11C11/5671 , G11C13/0033 , G11C13/0035 , G11C16/3431 , G11C16/349 , H03M13/1111 , H03M13/1515 , H03M13/152 , H03M13/3738 , H03M13/41 , H03M13/4138
Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.
Abstract translation: 在一个实施例中，编码器从存储器单元读取一组数据，以获得受到一个或多个失真机制影响的检索数据，作为已被存储的结果。 响应于检索到的数据生成质量度量，该数据响应于用户数据和相关联的检索数据之间的差异而改变值。 质量监视器建立质量度量的当前值与阈值之间的关系，并且将关系监视为指示检索数据质量的劣化，并且选择性地启动错误响应。 在另一个实施例中，当监视质量度量时，校正值被迭代通过一组值，使得可以选择最紧密接近数据的初始写入之后的质量度量值的质量度量的值 。
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8.发明申请CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY 有权用于访问面向对象非易失性存储器的控制装置和方法公开(公告)号：US20140156916A1
公开(公告)日：2014-06-05
申请号：US14092731
申请日：2013-11-27
Applicant: Micron Technology, Inc.
Inventor： Stephen P. Van Aken
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/1028 , G06F2212/7201 , G06F2212/7205 , G06F2212/7206 , G06F2212/7207 , G06F2212/7211 , Y02D10/13
Abstract: A read/write arrangement is described for use in accessing at least one nonvolatile memory device in read/write operations with the memory device being made up of a plurality of memory cells which memory cells are organized as a set of pages that are physically and sequentially addressable with each page having a page length such that a page boundary is defined between successive ones of the pages in the set. The read/write arrangement includes a control arrangement that is configured to store and access a group of data blocks that is associated with a given write operation in a successive series of pages of the memory such that at least an initial page in the series is filled and each block includes a block length that is different than the page length.
Abstract translation: 描述了用于在读/写操作中访问至少一个非易失性存储器件的读/写布置，其中存储器件由多个存储器单元构成，这些存储器单元被组织为物理和顺序的一组页 可寻址，每个页面具有页面长度，使得页面边界在集合中的连续的页面之间被定义。 读/写布置包括控制装置，其被配置为存储和访问与存储器的连续一系列页面中的给定写入操作相关联的一组数据块，使得该系列中的至少初始页面被填充 并且每个块包括与页长度不同的块长度。
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公开(公告)号：US20140093076A1
公开(公告)日：2014-04-03
申请号：US14096436
申请日：2013-12-04
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Stephen P. Van Aken , Gerald L. Cadloni , John L. Seabury , Robert B. Eisenhuth
IPC: H04L29/06
CPC classification number: H04L1/0041 , G06F11/1072 , H03M13/253 , H03M13/2936 , H03M13/353 , H04L63/0428
Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
Abstract translation: 系统使用多级编码，其中多个符号的每个符号表示用于使用多级传输信道传送的用户数据符号流中的多于一位的信息。 以数字逐位形式表示用户数据符号，使得每个符号被呈现为多个位，并且每个位受到不同的误差概率。 基于与多个中的每个位相关联的不同误差概率应用纠错过程。 通道可被配置为支持马赛克瓦片结构，每个瓦片包含通道符号，使得所选择的瓦片具有与其他瓦片不同的集体误差概率。 可以将定制编码应用于瓦片结构，以基于总体可用校正功率将所选量的误差校正功率分配给所选择的瓦片。
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公开(公告)号：US10068109B2
公开(公告)日：2018-09-04
申请号：US15829718
申请日：2017-12-01
Applicant: Micron Technology, Inc.
Inventor： Kenny T. Coker , David A. Pohm , Stephen P. Van Aken , Michael B. Danielson
Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.
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