公开(公告)号：US20180151206A1

公开(公告)日：2018-05-31

申请号：US15859029

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Feng Q. Pan ,  Hernan A. Castro ,  DerChang Kau

IPC: G11C7/22 ,  G11C13/00 ,  G11C7/10 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1063 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/71

Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

公开(公告)号：US09905280B2

公开(公告)日：2018-02-27

申请号：US15490327

申请日：2017-04-18

Applicant: Micron Technology, Inc.

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Feng Q. Pan ,  Hernan A. Castro ,  DerChang Kau

IPC: G11C7/22 ,  G11C5/14 ,  G11C13/00

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1063 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/71

Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

公开(公告)号：US10431270B2

公开(公告)日：2019-10-01

申请号：US15859029

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Feng Q. Pan ,  Hernan A. Castro ,  DerChang Kau

IPC: G11C13/00 ,  G11C7/22 ,  G11C5/14 ,  G11C7/10

Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

公开(公告)号：US09653127B1

公开(公告)日：2017-05-16

申请号：US14970380

申请日：2015-12-15

Applicant: Micron Technology, Inc.

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Feng Q. Pan ,  Hernan A. Castro ,  DerChang Kau

IPC: G11C5/14

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1063 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/71

Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.

公开(公告)号：US20170221536A1

公开(公告)日：2017-08-03

申请号：US15490327

申请日：2017-04-18

Applicant: Micron Technology, Inc.

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Feng Q. Pan ,  Hernan A. Castro ,  DerChang Kau

IPC: G11C7/22 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1063 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/71

Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.