公开(公告)号：US20220199180A1

公开(公告)日：2022-06-23

申请号：US17248728

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Eleuterio Mannella ,  Massimo Rossini

IPC: G11C29/38 ,  G06F1/04

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

公开(公告)号：US20240257892A1

公开(公告)日：2024-08-01

申请号：US18630895

申请日：2024-04-09

Applicant: Micron Technology, Inc.

Inventor： Eleuterio Mannella ,  Massimo Rossini

IPC: G11C29/38 ,  G06F1/04 ,  G06F1/26

CPC classification number: G11C29/38 ,  G06F1/04 ,  G06F1/26

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

公开(公告)号：US11990197B2

公开(公告)日：2024-05-21

申请号：US17248728

申请日：2021-02-04

Applicant: Micron Technology, Inc.

Inventor： Eleuterio Mannella ,  Massimo Rossini

IPC: G11C29/38 ,  G06F1/04 ,  G06F1/26

CPC classification number: G11C29/38 ,  G06F1/04 ,  G06F1/26

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.