ESTIMATING RESISTANCE-CAPACITANCE TIME CONSTANT OF ELECTRICAL CIRCUIT

    公开(公告)号:US20220293182A1

    公开(公告)日:2022-09-15

    申请号:US17832117

    申请日:2022-06-03

    Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

    Estimating resistance-capacitance time constant of electrical circuit

    公开(公告)号:US11615846B2

    公开(公告)日:2023-03-28

    申请号:US17832117

    申请日:2022-06-03

    Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

    Dynamic program window determination in a memory device
    4.
    发明授权
    Dynamic program window determination in a memory device 有权
    在存储设备中动态程序窗口确定

    公开(公告)号:US09305659B2

    公开(公告)日:2016-04-05

    申请号:US14826298

    申请日:2015-08-14

    Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

    Abstract translation: 存储器件具有存储器单元的阵列和耦合到存储器单元阵列的控制器。 控制器被配置为在执行对存储器件执行的特定编程操作的一部分之后以及在执行对存储器件执行的特定编程操作的后续部分之后确定程序窗口。 控制器被配置为响应于由存储器单元的特定状态经历的程序干扰的量来确定程序窗口。 控制器被配置为使用所确定的程序窗口来执行在存储器设备上执行的特定编程操作的后续部分。

    PEAK POWER MANAGEMENT CONNECTIVITY CHECK IN A MEMORY DEVICE

    公开(公告)号:US20220199180A1

    公开(公告)日:2022-06-23

    申请号:US17248728

    申请日:2021-02-04

    Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

    Dynamic program window determination in a memory device
    6.
    发明授权
    Dynamic program window determination in a memory device 有权
    在存储设备中动态程序窗口确定

    公开(公告)号:US09455043B2

    公开(公告)日:2016-09-27

    申请号:US15075768

    申请日:2016-03-21

    Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

    Abstract translation: 存储器件具有控制器。 控制器被配置为使得存储器件禁止对一组存储器单元进行编程。 控制器被配置为使存储器件施加编程脉冲来控制该组存储器单元的栅极。 控制器被配置为确定响应于编程脉冲的存储器单元组经历的干扰量。 控制器被配置为响应于干扰量来确定程序窗口。

    PEAK POWER MANAGEMENT CONNECTIVITY CHECK IN A MEMORY DEVICE

    公开(公告)号:US20240257892A1

    公开(公告)日:2024-08-01

    申请号:US18630895

    申请日:2024-04-09

    CPC classification number: G11C29/38 G06F1/04 G06F1/26

    Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

    Peak power management connectivity check in a memory device

    公开(公告)号:US11990197B2

    公开(公告)日:2024-05-21

    申请号:US17248728

    申请日:2021-02-04

    CPC classification number: G11C29/38 G06F1/04 G06F1/26

    Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

    DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE
    9.
    发明申请
    DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE 有权
    记忆设备中的动态程序窗口确定

    公开(公告)号:US20160203875A1

    公开(公告)日:2016-07-14

    申请号:US15075768

    申请日:2016-03-21

    Abstract: A memory device has a controller. The controller is configured to cause the memory device to inhibit programming of a group of memory cells. The controller is configured to cause the memory device to apply a programming pulse to control gates of the group of memory cells. The controller is configured to determine an amount of disturb experienced by the group of memory cells responsive to the programming pulse. The controller is configured to determine a program window responsive to the amount of disturb.

    Abstract translation: 存储器件具有控制器。 控制器被配置为使得存储器件禁止对一组存储器单元进行编程。 控制器被配置为使存储器件施加编程脉冲来控制该组存储器单元的栅极。 控制器被配置为确定响应于编程脉冲的存储器单元组经历的干扰量。 控制器被配置为响应于干扰量来确定程序窗口。

    DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE
    10.
    发明申请
    DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE 有权
    记忆设备中的动态程序窗口确定

    公开(公告)号:US20150348643A1

    公开(公告)日:2015-12-03

    申请号:US14826298

    申请日:2015-08-14

    Abstract: A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window after a portion of a particular programing operation performed on the memory device is performed and before a subsequent portion of the particular programing operation performed on the memory device is performed. The controller is configured to determine the program window responsive to an amount of program disturb experienced by a particular state of a memory cell. The controller is configured to perform the subsequent portion of the particular programing operation performed on the memory device using the determined program window.

    Abstract translation: 存储器件具有存储器单元的阵列和耦合到存储器单元阵列的控制器。 控制器被配置为在执行对存储器件执行的特定编程操作的一部分之后以及在执行对存储器件执行的特定编程操作的后续部分之后确定程序窗口。 控制器被配置为响应于由存储器单元的特定状态经历的程序干扰的量来确定程序窗口。 控制器被配置为使用所确定的程序窗口来执行在存储器设备上执行的特定编程操作的后续部分。

Patent Agency Ranking