公开(公告)号：US10121734B2

公开(公告)日：2018-11-06

申请号：US15001255

申请日：2016-01-20

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US11062984B2

公开(公告)日：2021-07-13

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01K3/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US20190074246A1

公开(公告)日：2019-03-07

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.