公开(公告)号：US10121734B2

公开(公告)日：2018-11-06

申请号：US15001255

申请日：2016-01-20

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US20190074246A1

公开(公告)日：2019-03-07

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US09865516B2

公开(公告)日：2018-01-09

申请号：US14992013

申请日：2016-01-10

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Chun-Yi Wu ,  Sheng-Yu Yan ,  Yi-Ting Cheng

IPC: H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L22/32 ,  H01L21/7685 ,  H01L21/76892 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05005 ,  H01L2224/06102 ,  H01L2924/2064

Abstract: A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (WAT) pad in the scribe-line region of the wafer. A top surface of the WAT pad is lower than a top surface of the conductive bonding pad.

公开(公告)号：US11062984B2

公开(公告)日：2021-07-13

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01K3/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US09735119B1

公开(公告)日：2017-08-15

申请号：US15219265

申请日：2016-07-25

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L24/03 ,  H01L22/32 ,  H01L23/488 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/43 ,  H01L24/46 ,  H01L24/85 ,  H01L2224/05124 ,  H01L2224/05567 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/00014

Abstract: In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.