公开(公告)号：US10446509B2

公开(公告)日：2019-10-15

申请号：US16039652

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US20190074246A1

公开(公告)日：2019-03-07

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US10043769B2

公开(公告)日：2018-08-07

申请号：US14730231

申请日：2015-06-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US10566229B2

公开(公告)日：2020-02-18

申请号：US15910360

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US11735540B2

公开(公告)日：2023-08-22

申请号：US17177431

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L25/00

CPC classification number: H01L24/02 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/97 ,  H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

公开(公告)号：US10121734B2

公开(公告)日：2018-11-06

申请号：US15001255

申请日：2016-01-20

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US09916999B2

公开(公告)日：2018-03-13

申请号：US14731380

申请日：2015-06-04

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68363 ,  H01L2924/00014

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US09748106B2

公开(公告)日：2017-08-29

申请号：US15002405

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Yi-Jen Lo ,  Neng-Tai Shih

IPC: H01L21/38 ,  H01L21/304 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/304 ,  H01L21/76898 ,  H01L21/78

Abstract: A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.

公开(公告)号：US20170213740A1

公开(公告)日：2017-07-27

申请号：US15002405

申请日：2016-01-21

Applicant: Micron Technology, Inc.

Inventor： Yi-Jen Lo ,  Neng-Tai Shih

IPC: H01L21/304 ,  H01L21/78 ,  H01L21/768

CPC classification number: H01L21/304 ,  H01L21/76898 ,  H01L21/78

Abstract: A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the conductive via.

公开(公告)号：US20210175188A1

公开(公告)日：2021-06-10

申请号：US17177431

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.