公开(公告)号：US10566229B2

公开(公告)日：2020-02-18

申请号：US15910360

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20190074246A1

公开(公告)日：2019-03-07

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US09748184B2

公开(公告)日：2017-08-29

申请号：US14883632

申请日：2015-10-15

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/585 ,  H01L21/6835 ,  H01L21/6836 ,  H01L22/14 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/552 ,  H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.

公开(公告)号：US20180190761A1

公开(公告)日：2018-07-05

申请号：US15396828

申请日：2017-01-03

Applicant: Micron Technology, Inc.

Inventor： Hsu Chiang ,  Neng-Tai Shih ,  Tieh-Chiang Wu

IPC: H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/288 ,  H01L21/027

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A metal-insulator-metal (MIM) capacitor is disclosed. The MIM capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. The bottom electrode includes a metal plate and a three-dimensional (3D) metal structure protruding from a top surface of the metal plate. A second dielectric layer surrounds the 3D metal structure. A capacitor dielectric layer covers the 3D metal structure and the second dielectric layer. A top electrode is disposed on the capacitor dielectric layer. The top electrode has fins that interdigitate with the 3D metal structure.

公开(公告)号：US10121734B2

公开(公告)日：2018-11-06

申请号：US15001255

申请日：2016-01-20

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US09916999B2

公开(公告)日：2018-03-13

申请号：US14731380

申请日：2015-06-04

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68363 ,  H01L2924/00014

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US11062984B2

公开(公告)日：2021-07-13

申请号：US16177891

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Hsu Chiang ,  Hsin-Chuan Tsai ,  Sheng-Hsiung Wu

IPC: H01K3/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

公开(公告)号：US10818536B2

公开(公告)日：2020-10-27

申请号：US16776343

申请日：2020-01-29

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20200168497A1

公开(公告)日：2020-05-28

申请号：US16776343

申请日：2020-01-29

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20180190531A1

公开(公告)日：2018-07-05

申请号：US15910360

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L21/78

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68363 ,  H01L2924/00014

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.