公开(公告)号：US09099472B2

公开(公告)日：2015-08-04

申请号：US14063981

申请日：2013-10-25

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Hung Ming Tsai ,  Duane M. Goodner

IPC: H01L23/532 ,  C23C16/04 ,  H01L27/108 ,  H01L21/74 ,  H01L21/768

CPC classification number: H01L23/53252 ,  C23C16/045 ,  H01L21/743 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.

Abstract translation: 一些实施例包括形成导电结构的方法。 可以用第一沉积方法沉积导电材料。 第一沉积方法具有第一沉积速率并形成导电结构的第一部分。 导电结构的第二部分可以通过用具有第二沉积速率的第二沉积方法沉积导电材料来形成。 第二沉积速率可以不同于第一沉积速率至少约3倍。在一些实施例中，导电结构的区域用作DRAM单元的晶体管栅极。 一些实施例包括半导体结构。

公开(公告)号：US20150303147A1

公开(公告)日：2015-10-22

申请号：US14752680

申请日：2015-06-26

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Hung Ming Tsai ,  Duane M. Goodner

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53252 ,  C23C16/045 ,  H01L21/743 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.

Abstract translation: 一些实施例包括形成导电结构的方法。 可以用第一沉积方法沉积导电材料。 第一沉积方法具有第一沉积速率并形成导电结构的第一部分。 导电结构的第二部分可以通过用具有第二沉积速率的第二沉积方法沉积导电材料来形成。 第二沉积速率可以不同于第一沉积速率至少约3倍。在一些实施例中，导电结构的区域用作DRAM单元的晶体管栅极。 一些实施例包括半导体结构。

公开(公告)号：US20140048943A1

公开(公告)日：2014-02-20

申请号：US14063981

申请日：2013-10-25

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Hung Ming Tsai ,  Duane M. Goodner

IPC: H01L23/532

CPC classification number: H01L23/53252 ,  C23C16/045 ,  H01L21/743 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.

Abstract translation: 一些实施例包括形成导电结构的方法。 可以用第一沉积方法沉积导电材料。 第一沉积方法具有第一沉积速率并形成导电结构的第一部分。 导电结构的第二部分可以通过用具有第二沉积速率的第二沉积方法沉积导电材料来形成。 第二沉积速率可以不同于第一沉积速率至少约3倍。在一些实施例中，导电结构的区域用作DRAM单元的晶体管栅极。 一些实施例包括半导体结构。