公开(公告)号：US09812455B2

公开(公告)日：2017-11-07

申请号：US15218487

申请日：2016-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

IPC: H01L27/108 ,  H01L21/768 ,  H01L49/02 ,  H01L21/3213

CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

公开(公告)号：US20160336325A1

公开(公告)日：2016-11-17

申请号：US15218487

申请日：2016-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

公开(公告)号：US09589962B2

公开(公告)日：2017-03-07

申请号：US14307121

申请日：2014-06-17

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

IPC: H01L21/768 ,  H01L27/108 ,  H01L49/02 ,  H01L21/3213

CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

Abstract translation: 形成导电通孔的方法包括在衬底上垂直地形成至少三个平行线结构。 线结构单独地包括电介质顶部和电介质侧壁。 导线在垂直方向上形成并相对于线结构形成。 导线包括纵向连续部分和多个导电材料延伸部，其在紧邻的线结构之间分别向内垂直延伸。 蚀刻通过纵向连续部分垂直地进行，并且沿着导电线在间隔开的位置部分地垂直地延伸到延伸部分中，以分解纵向连续部分，以形成在紧邻线结构之间垂直延伸的单个导电通孔。 还公开了形成存储器阵列的方法。 还公开了与制造方法无关的导电通孔的阵列。

公开(公告)号：US20150364414A1

公开(公告)日：2015-12-17

申请号：US14307121

申请日：2014-06-17

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

Abstract translation: 形成导电通孔的方法包括在衬底上垂直地形成至少三个平行线结构。 线结构单独地包括电介质顶部和电介质侧壁。 导线在垂直方向上形成并相对于线结构形成。 导线包括纵向连续部分和多个导电材料延伸部，其在紧邻的线结构之间分别向内垂直延伸。 蚀刻通过纵向连续部分垂直地进行，并且沿着导电线在间隔开的位置部分地垂直地延伸到延伸部分中，以分解纵向连续部分，以形成在紧邻线结构之间垂直延伸的单个导电通孔。 还公开了形成存储器阵列的方法。 还公开了与制造方法无关的导电通孔的阵列。