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    Electrically conductive lines and integrated circuitry comprising a line of recessed access devices
    3.
    发明授权
    Electrically conductive lines and integrated circuitry comprising a line of recessed access devices 有权
    导电线路和集成电路，包括一系列凹入的接入设备

    公开(公告)号：US08957483B2

    公开(公告)日：2015-02-17

    申请号：US13910280

    申请日：2013-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Brent Gilgen

    IPC: H01L27/088 ,  H01L23/48 ,  H01L21/74 ,  H01L23/535 ,  H01L29/78

    CPC classification number: H01L21/743 ,  H01L23/48 ,  H01L23/535 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.

    Abstract translation: 形成导电掩埋线及其电接触的方法包括在衬底材料的沟槽内形成纵向细长的导电线。 沟槽内的纵向端部具有勺子形状，具有容器。 容器中填充有导电材料。 绝缘材料形成在容器内的导电材料上。 在位于容器内的导电材料上形成接触开口。 导体材料形成在接触开口中，与位于容器内的第二导电材料电连接。 公开了其它方法和设备实现。

    Methods of forming electrically conductive lines
    5.
    发明授权
    Methods of forming electrically conductive lines 有权
    形成导电线的方法

    公开(公告)号：US09171750B2

    公开(公告)日：2015-10-27

    申请号：US14602598

    申请日：2015-01-22

    Applicant: Micron Technology, Inc.

    Inventor： Brent Gilgen

    IPC: H01L21/8234 ,  H01L21/74 ,  H01L23/535 ,  H01L23/48 ,  H01L29/78

    CPC classification number: H01L21/743 ,  H01L23/48 ,  H01L23/535 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.

    Abstract translation: 形成导电掩埋线及其电接触的方法包括在衬底材料的沟槽内形成纵向细长的导电线。 沟槽内的纵向端部具有勺子形状，具有容器。 容器中填充有导电材料。 绝缘材料形成在容器内的导电材料上。 在位于容器内的导电材料上形成接触开口。 导体材料形成在接触开口中，与位于容器内的第二导电材料电连接。 公开了其它方法和设备实现。

    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
    6.
    发明授权
    Methods of forming an elevationally extending conductor laterally between a pair of conductive lines 有权

    公开(公告)号：US10134741B2

    公开(公告)日：2018-11-20

    申请号：US15652724

    申请日：2017-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

    IPC: H01L21/768 ,  H01L27/108

    Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

    Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
    8.
    发明授权
    Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias 有权
    导电通孔的阵列，形成存储器阵列的方法以及形成导电通孔的方法

    公开(公告)号：US09589962B2

    公开(公告)日：2017-03-07

    申请号：US14307121

    申请日：2014-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

    IPC: H01L21/768 ,  H01L27/108 ,  H01L49/02 ,  H01L21/3213

    CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

    Abstract translation: 形成导电通孔的方法包括在衬底上垂直地形成至少三个平行线结构。 线结构单独地包括电介质顶部和电介质侧壁。 导线在垂直方向上形成并相对于线结构形成。 导线包括纵向连续部分和多个导电材料延伸部，其在紧邻的线结构之间分别向内垂直延伸。 蚀刻通过纵向连续部分垂直地进行，并且沿着导电线在间隔开的位置部分地垂直地延伸到延伸部分中，以分解纵向连续部分，以形成在紧邻线结构之间垂直延伸的单个导电通孔。 还公开了形成存储器阵列的方法。 还公开了与制造方法无关的导电通孔的阵列。

    Array Of Conductive Vias, Methods Of Forming A Memory Array, And Methods Of Forming Conductive Vias
    9.
    发明申请
    Array Of Conductive Vias, Methods Of Forming A Memory Array, And Methods Of Forming Conductive Vias 有权
    导电通孔阵列，形成存储器阵列的方法和形成导电通孔的方法

    公开(公告)号：US20150364414A1

    公开(公告)日：2015-12-17

    申请号：US14307121

    申请日：2014-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Wolfgang Mueller ,  Brent Gilgen ,  Dylan R. Macmaster ,  Jim A. Jozwiak

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L27/108 ,  H01L21/32133 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/90

    Abstract: A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions individually comprise a dielectric top and dielectric sidewalls. A conductive line is formed elevationally over and angles relative to the line constructions. The conductive line comprises a longitudinally continuous portion and a plurality of conductive material extensions that individually extend elevationally inward between immediately adjacent of the line constructions. Etching is conducted elevationally through the longitudinally continuous portion and partially elevationally into the extensions at spaced locations along the conductive line to break-up the longitudinally continuous portion to form individual conductive vias extending elevationally between immediately adjacent of the line constructions. Methods of forming a memory array are also disclosed. Arrays of conductive vias independent of method of manufacture are also disclosed.

    Abstract translation: 形成导电通孔的方法包括在衬底上垂直地形成至少三个平行线结构。 线结构单独地包括电介质顶部和电介质侧壁。 导线在垂直方向上形成并相对于线结构形成。 导线包括纵向连续部分和多个导电材料延伸部，其在紧邻的线结构之间分别向内垂直延伸。 蚀刻通过纵向连续部分垂直地进行，并且沿着导电线在间隔开的位置部分地垂直地延伸到延伸部分中，以分解纵向连续部分，以形成在紧邻线结构之间垂直延伸的单个导电通孔。 还公开了形成存储器阵列的方法。 还公开了与制造方法无关的导电通孔的阵列。

    Methods of Forming Electrically Conductive Lines Devices
    10.
    发明申请
    Methods of Forming Electrically Conductive Lines Devices 有权
    形成导电线路器件的方法

    公开(公告)号：US20150132934A1

    公开(公告)日：2015-05-14

    申请号：US14602598

    申请日：2015-01-22

    Applicant: Micron Technology, Inc.

    Inventor： Brent Gilgen

    IPC: H01L21/74 ,  H01L23/535

    CPC classification number: H01L21/743 ,  H01L23/48 ,  H01L23/535 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line within a trench in substrate material. A longitudinal end part thereof within the trench is of spoon-like shape having a receptacle. The receptacle is filled with conductive material. Insulative material is formed over the conductive material that is within the receptacle. A contact opening is formed over the conductive material that is within the receptacle. Conductor material is formed in the contact opening in electrical connection with the second conductive material that is within the receptacle. Other method and device implementations are disclosed.

    Abstract translation: 形成导电掩埋线及其电接触的方法包括在衬底材料的沟槽内形成纵向细长的导电线。 沟槽内的纵向端部具有勺子形状，具有容器。 容器中填充有导电材料。 绝缘材料形成在容器内的导电材料上。 在位于容器内的导电材料上形成接触开口。 导体材料形成在接触开口中，与位于容器内的第二导电材料电连接。 公开了其它方法和设备实现。

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