Techniques for determining memory cell read offsets

    公开(公告)号:US11158387B1

    公开(公告)日:2021-10-26

    申请号:US16941894

    申请日:2020-07-29

    Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

    Techniques for determining memory cell read offsets

    公开(公告)号:US11721398B2

    公开(公告)日:2023-08-08

    申请号:US17502497

    申请日:2021-10-15

    CPC classification number: G11C16/26 G11C11/5642 G11C11/5671

    Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

    MEMORY READ PERFORMANCE TECHNIQUES

    公开(公告)号:US20220300208A1

    公开(公告)日:2022-09-22

    申请号:US17631201

    申请日:2021-03-18

    Abstract: Methods, systems, and devices for memory read performance techniques are described. A memory system may receive a sequence of read commands. Based on detecting a set of consecutive read commands, the memory system may pre-read data from a second logical block address (LBA) in a non-volatile memory device to a volatile memory device based on receiving a first read command that includes a first LBA, where the second LBA is consecutive with the first LBA. The memory system may subsequently receive a second read command that includes the second LBA, and read out the second data without performing an additional access operation of the non-volatile storage device. In some examples, using such a pre-read, the memory system may capable of returning data in a different order than the order in which the commands were received.

    TECHNIQUES FOR DETERMINING MEMORY CELL READ OFFSETS

    公开(公告)号:US20220108753A1

    公开(公告)日:2022-04-07

    申请号:US17502497

    申请日:2021-10-15

    Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

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