公开(公告)号：US20240347083A1

公开(公告)日：2024-10-17

申请号：US18614244

申请日：2024-03-22

Applicant: Micron Technology, Inc.

Inventor： Jie Yang ,  Xu Zhang ,  Bin Zhao

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1084 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/14

Abstract: Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.

公开(公告)号：US12050786B2

公开(公告)日：2024-07-30

申请号：US17628800

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Lingyun Wang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/1009

Abstract: Methods, systems, and devices for read operations for active regions of a memory device are described. A memory system that includes a non-volatile memory device may receive a command to enter a first power mode. Before entering the first power mode, the memory system may store an indication of the active regions of the non-volatile memory device that are active for use as part of a host performance booster (HPB) mode. The memory device may receive an HPB command while in the first power mode, and may subsequently enter (e.g., re-enter) the second power mode. In some examples, the HPB command may be processed based on its physical address being included in one of the active regions of the non-volatile memory device.

公开(公告)号：US20230367706A1

公开(公告)日：2023-11-16

申请号：US17629306

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Lingyun Wang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for managing regions of a memory system are described. A memory system may include a non-volatile memory device and may receive a host performance booster (HPB) command (e.g., a read command) associated with one or more regions of the non-volatile memory device. The memory system may determine whether the region(s) associated with the HPB command are active. In instances where one or more of the associated regions are inactive, the memory system may activate the region(s) and deactivate one or more other regions based on a recency parameter (e.g., a timing parameter). The memory system may process the received HPB command based on the associated region(s) being active.

公开(公告)号：US20230360682A1

公开(公告)日：2023-11-09

申请号：US17629600

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Jie Yang ,  Xu Zhang ,  Bin Zhao

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1084 ,  G11C7/1096 ,  G11C7/1069 ,  G11C7/14

Abstract: Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.

公开(公告)号：US20230359538A1

公开(公告)日：2023-11-09

申请号：US17597985

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Lingyun Wang

IPC: G06F11/30 ,  G06F11/34 ,  G06F12/0871

CPC classification number: G06F11/3037 ,  G06F11/3409 ,  G06F12/0871 ,  G06F2212/7201

Abstract: Methods, systems, and devices for performance benchmark for host performance booster are described. The memory system may receive a plurality of read commands from a host system. The memory system may detect a pattern of random physical addresses as part of the plurality of read commands and increase an amount of space in a cache of the memory system based on the detected pattern. In some cases, the amount of space may be used for mapping between logical block addresses and physical addresses. The memory system may determine, for a different plurality of read commands, whether a rate of cache hits for a portion of the mapping satisfies a threshold. In some cases, the memory system may determine whether to activate a host performance booster mode based on determining whether the rate of cache hits satisfies the threshold.

公开(公告)号：US12210447B2

公开(公告)日：2025-01-28

申请号：US17629306

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Lingyun Wang

IPC: G06F12/02

Abstract: Methods, systems, and devices for managing regions of a memory system are described. A memory system may include a non-volatile memory device and may receive a host performance booster (HPB) command (e.g., a read command) associated with one or more regions of the non-volatile memory device. The memory system may determine whether the region(s) associated with the HPB command are active. In instances where one or more of the associated regions are inactive, the memory system may activate the region(s) and deactivate one or more other regions based on a recency parameter (e.g., a timing parameter). The memory system may process the received HPB command based on the associated region(s) being active.

公开(公告)号：US20230350579A1

公开(公告)日：2023-11-02

申请号：US17637428

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liu Yang ,  Xiaolai Zhu ,  Bin Zhao

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

公开(公告)号：US20220300409A1

公开(公告)日：2022-09-22

申请号：US17272113

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Bin Zhao ,  Jianxiong Huang

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16

Abstract: Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.

公开(公告)号：US20230367491A1

公开(公告)日：2023-11-16

申请号：US17628800

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Lingyun Wang

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/1009

Abstract: Methods, systems, and devices for read operations for active regions of a memory device are described. A memory system that includes a non-volatile memory device may receive a command to enter a first power mode. Before entering the first power mode, the memory system may store an indication of the active regions of the non-volatile memory device that are active for use as part of a host performance booster (HPB) mode. The memory device may receive an HPB command while in the first power mode, and may subsequently enter (e.g., re-enter) the second power mode. In some examples, the HPB command may be processed based on its physical address being included in one of the active regions of the non-volatile memory device.

公开(公告)号：US20220300208A1

公开(公告)日：2022-09-22

申请号：US17631201

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Jingyuan Miao ,  Bin Zhao

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory read performance techniques are described. A memory system may receive a sequence of read commands. Based on detecting a set of consecutive read commands, the memory system may pre-read data from a second logical block address (LBA) in a non-volatile memory device to a volatile memory device based on receiving a first read command that includes a first LBA, where the second LBA is consecutive with the first LBA. The memory system may subsequently receive a second read command that includes the second LBA, and read out the second data without performing an additional access operation of the non-volatile storage device. In some examples, using such a pre-read, the memory system may capable of returning data in a different order than the order in which the commands were received.