公开(公告)号：US20180108396A1

公开(公告)日：2018-04-19

申请号：US15841131

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Koji Mine ,  Yoshifumi Mochida

IPC: G11C11/4076 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles: validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

公开(公告)号：US09865324B2

公开(公告)日：2018-01-09

申请号：US14887217

申请日：2015-10-19

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Koji Mine ,  Yoshifumi Mochida

IPC: G11C11/40 ,  G11C8/12 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4076 ,  G11C7/1039 ,  G11C7/109 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4096

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

公开(公告)号：US20170110173A1

公开(公告)日：2017-04-20

申请号：US14887217

申请日：2015-10-19

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Koji Mine ,  Yoshifumi Mochida

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/1039 ,  G11C7/109 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4096

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.

公开(公告)号：US10424367B2

公开(公告)日：2019-09-24

申请号：US15841131

申请日：2017-12-13

Applicant: Micron Technology, Inc.

Inventor： Hiroyuki Matsuno ,  Koji Mine ,  Yoshifumi Mochida

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C8/12

Abstract: Method and Apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle.