公开(公告)号：US20250024663A1

公开(公告)日：2025-01-16

申请号：US18747991

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vivek Yadav ,  Li Wei Fang

IPC: H10B12/00

Abstract: According to one or more embodiments of the disclosure, a method comprises: forming a first recess for a bit line contact structure of a semiconductor device; providing a liner on a surface of the first recess; etching the linear to open at least part of a bottom of the liner, forming a second recess under the first recess; performing an epitaxial growth process through the second recess; and providing a conductive material to the first and second recesses to form at least part of the bit line contact structure.

公开(公告)号：US20240334676A1

公开(公告)日：2024-10-03

申请号：US18427740

申请日：2024-01-30

Applicant: Micron Technology, Inc.

Inventor： Jay S. Brown ,  Protyush Sahu ,  Shuai Jia ,  Jeffery B. Hull ,  Silvia Borsari ,  Li Wei Fang ,  Vivek Y. Yadav ,  Jaidah Mohan

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/768

CPC classification number: H10B12/30 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/76897

Abstract: An apparatus comprises a memory array comprising access lines, digit lines, and memory cells. Each memory cell is coupled to an associated access line and an associated digit line and each memory cell comprises an access device, and a monocrystalline semiconductor material adjacent to the access device. A width of the monocrystalline semiconductor material is within a range of from about 8 nm to about 25 nm. Each memory cell comprises a metal silicide material over the monocrystalline semiconductor material, a metal contact material over the metal silicide material, and a storage node adjacent to the metal contact material. Methods of forming an apparatus and systems are also disclosed.

公开(公告)号：US20240172412A1

公开(公告)日：2024-05-23

申请号：US18241035

申请日：2023-08-31

Applicant: Micron Technology, Inc.

Inventor： Li Wei Fang ,  Vivek Yadav ,  Jordan D. Greenlee ,  Silvia Borsari

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Openings are formed through insulative material that is directly above the transistors and into the another source/drain regions. Individual of the openings are directly above individual of the another source/drain regions. A laterally-outer insulator material is formed in the individual openings within and below the insulative material. A laterally-inner insulator material is formed in the individual openings within and below the insulative material laterally-over the laterally-outer insulator material. The laterally-outer insulator material and the laterally-inner insulator material are directly against one another and have an interface there-between. The laterally-inner insulator material that is in the individual openings below the insulative material is removed. After such removing, conductor material is formed in the individual openings that is electrically coupled to one of the individual another source/drain regions. The laterally-outer insulator material, the laterally-inner insulator material, and the conductor material that are in the individual openings comprise individual conductive-via constructions. Digitlines are formed directly above the insulative material and that are individually electrically coupled to the conductor material of one of the individual conductive-via constructions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Structure is disclosed.