公开(公告)号：US20240347601A1

公开(公告)日：2024-10-17

申请号：US18634480

申请日：2024-04-12

Applicant: ENKRIS SEMICONDUCTOR, INC.

Inventor： Kai CHENG

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/04

CPC classification number: H01L29/1608 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02598 ,  H01L29/04

Abstract: The present disclosure provides a composite substrate including: a support layer; and a SiC monocrystalline layer on the support layer, where the SiC monocrystalline layer includes a first superjunction structure that includes first P-type layers and first N-type layers, and the first P-type layers and the first N-type layers extend inward along a thickness direction of the SiC monocrystalline layer from a surface of the SiC monocrystalline layer far from the support layer, and are alternately distributed in a direction parallel to a plane of the SiC monocrystalline layer.

公开(公告)号：US20240339319A1

公开(公告)日：2024-10-10

申请号：US18748489

申请日：2024-06-20

Applicant: ATOMERA INCORPORATED

Inventor： MAREK HYTHA ,  KEITH DORAN WEEKS ,  NYLES WYNN CODY ,  HIDEKI TAKEUCHI

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/02507 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/8234

Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

公开(公告)号：US20240334676A1

公开(公告)日：2024-10-03

申请号：US18427740

申请日：2024-01-30

Applicant: Micron Technology, Inc.

Inventor： Jay S. Brown ,  Protyush Sahu ,  Shuai Jia ,  Jeffery B. Hull ,  Silvia Borsari ,  Li Wei Fang ,  Vivek Y. Yadav ,  Jaidah Mohan

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/768

CPC classification number: H10B12/30 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/76897

Abstract: An apparatus comprises a memory array comprising access lines, digit lines, and memory cells. Each memory cell is coupled to an associated access line and an associated digit line and each memory cell comprises an access device, and a monocrystalline semiconductor material adjacent to the access device. A width of the monocrystalline semiconductor material is within a range of from about 8 nm to about 25 nm. Each memory cell comprises a metal silicide material over the monocrystalline semiconductor material, a metal contact material over the metal silicide material, and a storage node adjacent to the metal contact material. Methods of forming an apparatus and systems are also disclosed.

公开(公告)号：US20240243034A1

公开(公告)日：2024-07-18

申请号：US18623839

申请日：2024-04-01

Applicant: The Regents of the University of California

Inventor： Yongjie HU ,  Joon Sang KANG

IPC: H01L23/373 ,  C30B25/02 ,  C30B29/40 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L23/3738 ,  C30B25/02 ,  C30B29/40 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/20

Abstract: A device includes: (1) a boron arsenide substrate; and (2) an integrated circuit disposed in or over the boron arsenide substrate.

公开(公告)号：US20240194532A1

公开(公告)日：2024-06-13

申请号：US18080715

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L21/8221 ,  H01L21/02505 ,  H01L21/02598 ,  H01L21/31127 ,  H01L21/7688 ,  H01L24/16 ,  H01L24/29 ,  H01L25/074 ,  B82Y10/00

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

公开(公告)号：US20240141553A1

公开(公告)日：2024-05-02

申请号：US18191129

申请日：2023-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pu-Fang CHEN ,  Ching Yu Chen

IPC: C30B29/06 ,  C30B15/20 ,  C30B33/02 ,  H01L21/02

CPC classification number: C30B29/06 ,  C30B15/203 ,  C30B15/206 ,  C30B33/02 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02598

Abstract: A manufacturing process is described to evaluate and select raw semiconductor wafers in preparation for epitaxial layer formation. The manufacturing process first produces a single crystal ingot during which a seed pulling velocity and temperature gradient are closely controlled. The resulting ingot is vacancy-rich with relatively few self-interstitial defects. Selected wafers can advance to a high-temperature nitridation annealing operation that further reduces the number of interstitials while increasing the vacancies. Substrates characterized by a high vacancy density can then be used to optimize an epitaxial layer deposition process.

公开(公告)号：US11881486B2

公开(公告)日：2024-01-23

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/1211 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US11869803B2

公开(公告)日：2024-01-09

申请号：US17749282

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Byung Yoon Kim

IPC: H01L21/762 ,  H01L21/02 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/76251 ,  H01L21/02532 ,  H01L21/02598 ,  H01L25/18 ,  H01L25/50 ,  H01L21/02381

Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

公开(公告)号：US11810784B2

公开(公告)日：2023-11-07

申请号：US17236289

申请日：2021-04-21

Applicant: Atomera Incorporated

Inventor： Marek Hytha ,  Keith Doran Weeks ,  Nyles Wynn Cody ,  Hideki Takeuchi

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/02507 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/8234

Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

公开(公告)号：US20230352300A1

公开(公告)日：2023-11-02

申请号：US18304067

申请日：2023-04-20

Applicant: ASM IP Holding, B.V.

Inventor： Jan Deckers

IPC: C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/02 ,  C30B33/12

CPC classification number: H01L21/02507 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  C30B33/12 ,  H01L21/02444 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/0262 ,  H01J37/321

Abstract: Methods and systems for forming structures including a superlattice of silicon-containing epitaxial layers using nanoparticles. Exemplary methods can include forming nanoparticles in situ and depositing the nanoparticles onto a substrate surface to thereby form the epitaxial layers.