公开(公告)号：US20250024663A1

公开(公告)日：2025-01-16

申请号：US18747991

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vivek Yadav ,  Li Wei Fang

IPC: H10B12/00

Abstract: According to one or more embodiments of the disclosure, a method comprises: forming a first recess for a bit line contact structure of a semiconductor device; providing a liner on a surface of the first recess; etching the linear to open at least part of a bottom of the liner, forming a second recess under the first recess; performing an epitaxial growth process through the second recess; and providing a conductive material to the first and second recesses to form at least part of the bit line contact structure.

公开(公告)号：US20240172412A1

公开(公告)日：2024-05-23

申请号：US18241035

申请日：2023-08-31

Applicant: Micron Technology, Inc.

Inventor： Li Wei Fang ,  Vivek Yadav ,  Jordan D. Greenlee ,  Silvia Borsari

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Openings are formed through insulative material that is directly above the transistors and into the another source/drain regions. Individual of the openings are directly above individual of the another source/drain regions. A laterally-outer insulator material is formed in the individual openings within and below the insulative material. A laterally-inner insulator material is formed in the individual openings within and below the insulative material laterally-over the laterally-outer insulator material. The laterally-outer insulator material and the laterally-inner insulator material are directly against one another and have an interface there-between. The laterally-inner insulator material that is in the individual openings below the insulative material is removed. After such removing, conductor material is formed in the individual openings that is electrically coupled to one of the individual another source/drain regions. The laterally-outer insulator material, the laterally-inner insulator material, and the conductor material that are in the individual openings comprise individual conductive-via constructions. Digitlines are formed directly above the insulative material and that are individually electrically coupled to the conductor material of one of the individual conductive-via constructions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Structure is disclosed.

公开(公告)号：US20240389302A1

公开(公告)日：2024-11-21

申请号：US18658787

申请日：2024-05-08

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Chia Ying Lin ,  Davide Dorigo ,  Elisabeth Barr ,  Wan Rou Luo ,  Shi Han Wang ,  Sanjeev Sapra ,  Ashwin Panday ,  Vivek Yadav

IPC: H10B12/00

Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.

公开(公告)号：US20240074158A1

公开(公告)日：2024-02-29

申请号：US18234145

申请日：2023-08-15

Applicant: Micron Technology, Inc.

Inventor： Chunhua Yao ,  Song Guo ,  Vivek Yadav

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02

Abstract: A variety of applications can include an apparatus having a memory device in which, during fabrication of the memory device, processing a dielectric isolation region about an active area of a memory cell is controlled to provide enhanced electric isolation of a data line contact to the memory cell with respect to a cell contact to the memory cell. A portion of the dielectric isolation region can be recessed, creating a corner between the dielectric isolation region and a conductive region, where the conductive region is material for the active area. The corner can be filled with a dielectric material and the data line contact can be formed contacting the dielectric material and coupled to the conductive region. The cell contact can be formed to the memory cell contacting the dielectric material such that the dielectric material is between the cell contact and the data line contact.

公开(公告)号：US20230028297A1

公开(公告)日：2023-01-26

申请号：US17813076

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Silvia Borsari ,  Song Guo

IPC: H01L27/108

Abstract: A method of forming a semiconductor device comprising forming a silicon carbide material on a patterned material. The silicon carbide material is subjected to a plasma to expose horizontal portions of the silicon carbide material to the plasma. The horizontal portions of the silicon carbide material are selectively removed, and the patterned material is removed to form a pattern of the silicon carbide material.

公开(公告)号：US20230022071A1

公开(公告)日：2023-01-26

申请号：US17813080

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Chunhua Yao ,  Song Guo ,  Vivek Yadav

IPC: H01L27/108

Abstract: An apparatus comprising active areas and shallow trench isolation structures on a base material. A first conductive material is vertically adjacent to an active area of the active areas and between laterally adjacent shallow trench isolation structures. A second conductive material is vertically adjacent to the first conductive material and between the laterally adjacent shallow trench isolation structures. A silicon carbide material is on sidewalls of the shallow trench isolation structures and exhibits substantially vertical sidewalls. An oxide material is adjacent to the active areas and shallow trench isolation structures, a nitride material is adjacent to the oxide material, and a digit line is adjacent to the second conductive material. An electronic system and methods of forming an apparatus are also disclosed.

公开(公告)号：US11322388B2

公开(公告)日：2022-05-03

申请号：US16549594

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Shen Hu ,  Kangle Li ,  Sanjeev Sapra

IPC: H01L21/762 ,  H01L27/108 ,  H01L21/67 ,  H01L21/02

Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.

公开(公告)号：US20230354585A1

公开(公告)日：2023-11-02

申请号：US17731895

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Albert P. Chan ,  Sanjeev Sapra ,  Vivek Yadav ,  Yen Ting Lin ,  Devesh Dadhich Shreeram

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814

Abstract: Methods, apparatuses, and systems related to a digit line and cell contact are described. An example apparatus includes a semiconductor structure comprising a first layer comprising a first material on sidewalls of a plurality of patterned material. The apparatus further includes a second layer comprising a nitride material on sidewalls of the first layer. The apparatus further includes a third layer comprising the first material on sidewalls of the second layer. The apparatus further includes a base area, to provide digit line and cell contact isolation for the semiconductor structure. The apparatus further includes an active area, adjacent to the base area, that is adjacent to the semiconductor structure.

公开(公告)号：US11114443B2

公开(公告)日：2021-09-07

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/67 ,  H01L21/762

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.

公开(公告)号：US20210066307A1

公开(公告)日：2021-03-04

申请号：US16555565

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Vivek Yadav ,  Fatma Arzum Simsek-Ege ,  Sanjeev Sapra ,  Thomas A. Figura ,  Kangle Li

IPC: H01L27/108

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.