公开(公告)号：US11790974B2

公开(公告)日：2023-10-17

申请号：US17529182

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Markus Geiger ,  Randall Rooney

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/40622

Abstract: A memory device may enforce compliance with a refresh command requirement in some examples. When a controller fails to comply with the refresh command requirement, the memory device may prevent the controller from accessing a memory array. The controller may regain access by providing one or more commands, such as a refresh command. In some examples, the memory may enforce compliance with a refresh command requirement responsive to a value written to the mode register. In some examples, the memory may enforce compliance with the refresh command requirement after an initialization operation has completed.

公开(公告)号：US20230154519A1

公开(公告)日：2023-05-18

申请号：US17529182

申请日：2021-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Markus Geiger ,  Randall Rooney

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4072

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4072

Abstract: A memory device may enforce compliance with a refresh command requirement in some examples. When a controller fails to comply with the refresh command requirement, the memory device may prevent the controller from accessing a memory array. The controller may regain access by providing one or more commands, such as a refresh command. In some examples, the memory may enforce compliance with a refresh command requirement responsive to a value written to the mode register. In some examples, the memory may enforce compliance with the refresh command requirement after an initialization operation has completed.

公开(公告)号：US12230311B2

公开(公告)日：2025-02-18

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Cagdas Dirik ,  Robert M. Walker ,  Sujeet Ayyapureddi ,  Niccolo Izzo ,  Markus Geiger ,  Yang Lu ,  Ameen Akel ,  Elliott C. Cooper-Balis ,  Danilo Caraccio

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.