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    Interleaved cache prefetching
    1.
    发明授权
    Interleaved cache prefetching 有权

    公开(公告)号：US11886348B2

    公开(公告)日：2024-01-30

    申请号：US18117820

    申请日：2023-03-06

    申请人： Micron Technology, Inc.

    发明人： Laurent Isenegger ,  Robert M. Walker ,  Cagdas Dirik

    IPC分类号： G06F3/06 ,  G06F12/0862 ,  G06F12/0831

    CPC分类号： G06F12/0862 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0683 ,  G06F12/0835 ,  G06F2212/283

    摘要： A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

    DYNAMICALLY SIZED REDUNDANT WRITE BUFFER WITH SECTOR-BASED TRACKING
    3.
    发明申请
    DYNAMICALLY SIZED REDUNDANT WRITE BUFFER WITH SECTOR-BASED TRACKING 有权

    公开(公告)号：US20210357332A1

    公开(公告)日：2021-11-18

    申请号：US16876967

    申请日：2020-05-18

    申请人： Micron Technology, Inc.

    发明人： Cagdas Dirik ,  Robert M. Walker

    IPC分类号： G06F12/0891 ,  G06F12/0893 ,  G06F12/0815 ,  G06F13/16 ,  G06F11/07 ,  G06F11/30

    摘要： Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

    CACHE BUFFER
    4.
    发明申请
    CACHE BUFFER 审中-公开

    公开(公告)号：US20190065373A1

    公开(公告)日：2019-02-28

    申请号：US15690442

    申请日：2017-08-30

    申请人： Micron Technology, Inc.

    发明人： Cagdas Dirik ,  Robert M. Walker

    IPC分类号： G06F12/0831 ,  G06F13/16

    摘要： The present disclosure includes apparatuses and methods related to a cache buffer. An example apparatus can store data associated with a request in one of a number of buffers and service a subsequent request for data associated with the request using the one of the number of buffers. The subsequent request can be serviced while the request is being serviced by the cache controller.

    CACHE LINE DATA
    8.
    发明申请
    CACHE LINE DATA 审中-公开

    公开(公告)号：US20190065072A1

    公开(公告)日：2019-02-28

    申请号：US15690503

    申请日：2017-08-30

    申请人： Micron Technology, Inc.

    发明人： Cagdas Dirik ,  Robert M. Walker

    IPC分类号： G06F3/06 ,  G06F12/0868 ,  G06F12/0806 ,  G06F12/128

    摘要： The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible.