公开(公告)号：US20220057956A1

公开(公告)日：2022-02-24

申请号：US16997055

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Mingke Yu ,  Deping He

IPC: G06F3/06

Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and control circuit coupled with the first and second set of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

公开(公告)号：US11709617B2

公开(公告)日：2023-07-25

申请号：US16997055

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Mingke Yu ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.