公开(公告)号：US09646875B2

公开(公告)日：2017-05-09

申请号：US14931152

申请日：2015-11-03

Applicant: Micron Technology, Inc.

Inventor： Niccolo Righetti ,  Sara Vigano ,  Emelio Camerlenghi

IPC: H01L21/76 ,  H01L21/768 ,  H01L27/06 ,  H01L27/105

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

公开(公告)号：US20160056069A1

公开(公告)日：2016-02-25

申请号：US14931152

申请日：2015-11-03

Applicant: Micron Technology, Inc.

Inventor： Niccolo Righetti ,  Sara Vigano ,  Emelio Camerlenghi

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76877 ,  H01L27/0688 ,  H01L27/105

Abstract: Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry.

公开(公告)号：US20240231642A1

公开(公告)日：2024-07-11

申请号：US18407366

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Gianluca Nicosia ,  Akira Goda ,  Niccolo Righetti

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory sub-system with a memory device having a plurality of cells, and the plurality of cells having a set of cells, and a processing device operatively coupled to the memory device, the processing device to perform operations of determining a level information associated with the set of cells, where the set of cells comprise a target cell associated with a read operation, identifying a read level offset for the target cell based on the level information, and performing the read operation in accordance with the read level offset.