公开(公告)号：US20220350744A1

公开(公告)日：2022-11-03

申请号：US17723096

申请日：2022-04-18

Applicant: Micron Technology, Inc.

Inventor： Vanaja Urrinkala ,  Niraimathi N S

IPC: G06F12/0862

Abstract: Methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. Some memory systems may support pre-fetching information, such as logical-to-physical (L2P) mapping tables, data, or both, if a sequential pattern of read commands is detected. In some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. The list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching L2P mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

公开(公告)号：US20240231460A1

公开(公告)日：2024-07-11

申请号：US18536694

申请日：2023-12-12

Applicant: Micron Technology, Inc.

Inventor： Venkata Kiran Kumar Matturi ,  Sharath Chandra Ambula ,  Niraimathi N S

IPC: G06F1/28 ,  G06F1/10

CPC classification number: G06F1/28 ,  G06F1/10

Abstract: Information associated with a power consumption level of a set of components of a controller of a memory device is identified. A determination is made whether the information associated with the power consumption level satisfies one or more conditions. In response to the one or more conditions being satisfied, swallowing one or more clock pulses of a clock signal transmitted to at least one component of the set of components of the controller are swallowed.

公开(公告)号：US20250053515A1

公开(公告)日：2025-02-13

申请号：US18806224

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Vanaja Urrinkala ,  Niraimathi N S

IPC: G06F12/0862

Abstract: Methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. Some memory systems may support pre-fetching information, such as logical-to-physical (L2P) mapping tables, data, or both, if a sequential pattern of read commands is detected. In some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. The list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching L2P mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

公开(公告)号：US12079128B2

公开(公告)日：2024-09-03

申请号：US17723096

申请日：2022-04-18

Applicant: Micron Technology, Inc.

Inventor： Vanaja Urrinkala ,  Niraimathi N S

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6022

Abstract: Methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. Some memory systems may support pre-fetching information, such as logical-to-physical (L2P) mapping tables, data, or both, if a sequential pattern of read commands is detected. In some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. The list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. Additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching L2P mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.

公开(公告)号：US20230074643A1

公开(公告)日：2023-03-09

申请号：US17889660

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Kondalarao Chunchu ,  Niraimathi N S ,  Sharath Chandra Ambula ,  Shobhit Kumar Bhadani ,  Sushil Kumar ,  Vanaja Ambapuram ,  Venkata Kiran Kumar Matturi

IPC: G06F3/06

Abstract: Methods, systems, and devices for rate adjustments for a memory interface are described. A host system may communicate with a memory system via an interface according to multiple data transfer rates. For example, the host system may configure the interface to operate according to a first rate. The host system may switch the interface from the first rate to a second rate in response to one or more commands from the host system satisfying one or more parameters such as a threshold quantity of data associated with a command, a threshold quantity of issued commands associated with at least the threshold quantity of data, a threshold quantity of issued and unexecuted commands, or any combination thereof. Based on the switching, the host system may communicate with the memory system via the interface in accordance with the second rate.