公开(公告)号：US09276000B2

公开(公告)日：2016-03-01

申请号：US14010278

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Pierre C. Fazan

IPC: H01L21/8239 ,  H01L27/108 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L27/10805 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/10847 ,  H01L27/1203 ,  H01L29/7841

Abstract: Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.

公开(公告)号：US09093311B2

公开(公告)日：2015-07-28

申请号：US14299577

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Abstract translation: 公开了一种用于提供半导体存储器件的技术。 在一个实施例中，可以将技术实现为包括以行和列的阵列布置的多个存储单元的半导体存储器件。 每个存储器单元可以包括连接到以第一取向延伸的源极线的第一区域，连接到延伸第二取向的位线的第二区域以及与字线间隔开并且电容耦合到字线的主体区域，其中所述主体 区域是电浮动的并且设置在第一区域和第二区域之间。 半导体器件还可以包括沿阵列的第一取向延伸的第一阻挡壁和在阵列的第二取向延伸并且与第一阻挡壁相交的第二阻挡壁，以形成沟槽区域，该沟槽区域被配置为容纳多个 的记忆细胞。