公开(公告)号：US09093311B2

公开(公告)日：2015-07-28

申请号：US14299577

申请日：2014-06-09

Applicant: Micron Technology, Inc.

Inventor： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Abstract translation: 公开了一种用于提供半导体存储器件的技术。 在一个实施例中，可以将技术实现为包括以行和列的阵列布置的多个存储单元的半导体存储器件。 每个存储器单元可以包括连接到以第一取向延伸的源极线的第一区域，连接到延伸第二取向的位线的第二区域以及与字线间隔开并且电容耦合到字线的主体区域，其中所述主体 区域是电浮动的并且设置在第一区域和第二区域之间。 半导体器件还可以包括沿阵列的第一取向延伸的第一阻挡壁和在阵列的第二取向延伸并且与第一阻挡壁相交的第二阻挡壁，以形成沟槽区域，该沟槽区域被配置为容纳多个 的记忆细胞。

公开(公告)号：US09019759B2

公开(公告)日：2015-04-28

申请号：US14043833

申请日：2013-10-01

Applicant: Micron Technology, Inc.

Inventor： Srinivasa R. Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

IPC: G11C11/34 ,  G11C7/00 ,  H01L27/105 ,  H01L27/12 ,  H01L29/78 ,  H01L27/108

CPC classification number: H01L27/10802 ,  G11C7/00 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/7841

Abstract: Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

Abstract translation: 公开了一种用于提供半导体存储器件的技术。 在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。 每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。 每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

公开(公告)号：US08947965B2

公开(公告)日：2015-02-03

申请号：US13681151

申请日：2012-11-19

Applicant: Micron Technology Inc.

Inventor： Michael A. Van Buskirk ,  Betina Hold ,  Wayne Ellis

IPC: G11C11/34 ,  G11C16/26 ,  H01L27/108 ,  H01L29/73 ,  H01L29/78 ,  G11C11/402 ,  H01L27/102

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。 所述多个存储单元中的至少一个可以包括耦合到所述阵列的相应位线的第一区域，耦合到所述阵列的相应源极线的第二区域，与所述阵列间隔开并且电容耦合到相应单词的主体区域 阵列的线，其中所述主体区域可以是电浮置的并且设置在所述第一区域和所述第二区域之间，以及耦合到所述阵列的相应载体注入线的第三区域，其中所述相应的载体注入线可以是 阵列中的彼此耦合的多个载流子注入管线。

公开(公告)号：US08982633B2

公开(公告)日：2015-03-17

申请号：US13954660

申请日：2013-07-30

Applicant: Micron Technology, Inc.

Inventor： Srinivasa R. Banna ,  Michael A. Van Buskirk

IPC: G11C16/04 ,  G11C7/00 ,  G11C11/402 ,  G11C11/403 ,  H01L27/102 ,  H01L27/108 ,  H01L29/78 ,  H01L27/082

CPC classification number: G11C7/00 ,  G11C11/4026 ,  G11C11/403 ,  G11C2211/4016 ,  H01L27/082 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.

Abstract translation: 公开了提供直接注入半导体存储器件的技术。 在一个特定示例性实施例中，技术可以被实现为直接注入半导体存储器件，其包括连接到沿第一取向延伸的位线的第一区域和连接到沿第二取向延伸的源极线的第二区域。 直接注入半导体存储器件还可以包括与在第二取向上延伸的字线间隔开并且电容耦合到字线的主体区域，其中主体区域电浮置并且设置在第一区域和第二区域之间。 直接注入半导体存储器件还可以包括连接到沿着第二取向延伸的载流子注入管线的第三区域，其中第一区域，第二区域，体区域和第三区域以顺序连续的关系设置。