公开(公告)号：US12219750B2

公开(公告)日：2025-02-04

申请号：US18244069

申请日：2023-09-08

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: G11C11/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  H01L29/24 ,  H10B12/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US20170140833A1

公开(公告)日：2017-05-18

申请号：US14943541

申请日：2015-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/14

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

公开(公告)号：US10153049B2

公开(公告)日：2018-12-11

申请号：US15722188

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian Caillat ,  Akira Goda

IPC: G11C16/10 ,  G11C8/12 ,  G11C16/34 ,  G11C16/14 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

公开(公告)号：US10147494B2

公开(公告)日：2018-12-04

申请号：US15933498

申请日：2018-03-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.

公开(公告)号：US09953718B2

公开(公告)日：2018-04-24

申请号：US15437584

申请日：2017-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

公开(公告)号：US20240038322A1

公开(公告)日：2024-02-01

申请号：US17873991

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

公开(公告)号：US20230422471A1

公开(公告)日：2023-12-28

申请号：US18244069

申请日：2023-09-08

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: H10B12/00 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: H10B12/20 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4094 ,  H10B12/50 ,  H10B41/10

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US20230031904A1

公开(公告)日：2023-02-02

申请号：US17388678

申请日：2021-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: H01L27/108 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US20180068737A1

公开(公告)日：2018-03-08

申请号：US15722188

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

公开(公告)号：US12288592B2

公开(公告)日：2025-04-29

申请号：US17873991

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

IPC: G11C29/50

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.