公开(公告)号：US20210406166A1

公开(公告)日：2021-12-30

申请号：US16913304

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield ,  Richard D. Maes

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/16 ,  G06F13/42 ,  G06F9/38 ,  G06F7/57 ,  G06F11/10

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

公开(公告)号：US11481317B2

公开(公告)日：2022-10-25

申请号：US16913304

申请日：2020-06-26

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield ,  Richard D. Maes

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/16 ,  G06F11/10 ,  G06F9/38 ,  G06F7/57 ,  G06F13/42

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

公开(公告)号：US12189524B2

公开(公告)日：2025-01-07

申请号：US17960477

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield ,  Richard D. Maes

IPC: G06F12/02 ,  G06F7/57 ,  G06F9/38 ,  G06F11/10 ,  G06F12/0868 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

公开(公告)号：US20230025291A1

公开(公告)日：2023-01-26

申请号：US17960477

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Allan Porterfield ,  Richard D. Maes

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/16 ,  G06F11/10 ,  G06F9/38 ,  G06F7/57 ,  G06F13/42

Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.