-
公开(公告)号：US20210406166A1
公开(公告)日：2021-12-30
申请号：US16913304
申请日：2020-06-26
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield , Richard D. Maes
Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.
-
公开(公告)号：US20210049116A1
公开(公告)日：2021-02-18
申请号：US16537998
申请日：2019-08-12
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield
Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices coupled to one another. Each of the plurality of computing devices can include a processing unit configured to perform an operation on a block of data in response to receipt of the block of data. Each of the plurality of computing devices can further include a memory array configured as a cache for the processing unit. The example apparatus can further include a first plurality of communication subsystems coupled to the plurality of computing devices and to a second plurality of communication subsystems. The first and second plurality of communication subsystems are configured to request and/or transfer the block of data.
-
公开(公告)号：US11789653B2
公开(公告)日：2023-10-17
申请号：US17407927
申请日：2021-08-20
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/068 , G06F9/45558 , G06F2009/45583
Abstract: Memory access control, as described herein, can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example method for memory access control can include receiving, by control circuitry resident on a memory device, a memory access request targeting an address of a volatile (e.g., non-persistent) memory component of the memory device and determining characteristics of data associated with the targeted address. The method can further include accessing data at the targeted address of the volatile memory component in response to determining that the characteristics of the data meet a first criterion and accessing data at another address of a non-volatile memory component in response to determining that the characteristics of the data meet a second criterion.
-
公开(公告)号：US11768614B2
公开(公告)日：2023-09-26
申请号：US17169138
申请日：2021-02-05
Applicant: Micron Technology, Inc.
Inventor： Richard C. Murphy , Glen E. Hush , Vijay S. Ramesh , Allan Porterfield , Anton Korzh
IPC: G06F12/00 , G06F3/06 , G06F12/0868 , G06F12/02
CPC classification number: G06F3/0626 , G06F3/061 , G06F3/064 , G06F3/0631 , G06F3/0658 , G06F3/0661 , G06F12/0246 , G06F12/0868 , G06F2212/1016
Abstract: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.
-
公开(公告)号：US20210311799A1
公开(公告)日：2021-10-07
申请号：US16838272
申请日：2020-04-02
Applicant: Micron Technology, Inc.
Inventor： Allan Porterfield , Vijay S. Ramesh
Abstract: An example method corresponding to workload allocation among hardware devices can include monitoring, by a processing unit, workload characteristics associated with execution of workloads by a plurality of hardware devices, such as hardware accelerators. The method can include determining, by the processing unit, particular characteristics corresponding to a workload processed by at least one of the hardware devices and performing, by the processing unit, an action to determine that a particular hardware device exhibits higher performance in executing the workload than a different hardware device. The method can further include allocating a subsequent workload that has characteristics corresponding to the workload exhibiting the particular characteristics to the hardware device that exhibits higher performance in executing the workload than a different hardware device.
-
Patent Agency Ranking
公开(公告)号：US20210225443A1
公开(公告)日：2021-07-22
申请号：US17109999
申请日：2020-12-02
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield
Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.
-
公开(公告)号：US12189524B2
公开(公告)日：2025-01-07
申请号：US17960477
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield , Richard D. Maes
Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.
-
公开(公告)号：US11810618B2
公开(公告)日：2023-11-07
申请号：US17453136
申请日：2021-11-01
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield
CPC classification number: G11C13/0023 , G06F7/57 , G06F9/3001 , G06F9/542 , G06F9/546 , G11C13/004 , G11C13/0069 , G11C2213/71
Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.
-
公开(公告)号：US11579882B2
公开(公告)日：2023-02-14
申请号：US17212330
申请日：2021-03-25
Applicant: Micron Technology, Inc.
Inventor： Richard C. Murphy , Glen E. Hush , Vijay S. Ramesh , Allan Porterfield , Anton Korzh
Abstract: Systems, apparatuses, and methods related to extended memory operations are described. Extended memory operations can include operations specified by a single address and operand and may be performed by a computing device that includes a processing unit and a memory resource. The computing device can perform extended memory operations on data streamed through the computing tile without receipt of intervening commands. In an example, a computing device is configured to receive a command to perform an operation that comprises performing an operation on a data with the processing unit of the computing device and determine that an operand corresponding to the operation is stored in the memory resource. The computing device can further perform the operation using the operand stored in the memory resource.
-
公开(公告)号：US20230025291A1
公开(公告)日：2023-01-26
申请号：US17960477
申请日：2022-10-05
Applicant: Micron Technology, Inc.
Inventor： Vijay S. Ramesh , Allan Porterfield , Richard D. Maes
Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.025 seconds)
