公开(公告)号：US08546215B2

公开(公告)日：2013-10-01

申请号：US13781862

申请日：2013-03-01

Applicant: Micron Technology, Inc.

Inventor： Gordon Haller ,  Sanh Dang Tang ,  Steve Cummings

IPC: H01L29/94

CPC classification number: H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

公开(公告)号：US09117928B2

公开(公告)日：2015-08-25

申请号：US14188536

申请日：2014-02-24

Applicant: Micron Technology, Inc.

Inventor： John Zahurak ,  Sanh Dang Tang ,  Gurtej S. Sandhu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

Abstract translation: 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。

公开(公告)号：US20130178025A1

公开(公告)日：2013-07-11

申请号：US13781862

申请日：2013-03-01

Applicant: Micron Technology, Inc.

Inventor： Gordon Haller ,  Sanh Dang Tang ,  Steve Cummings

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract translation: 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。 在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

公开(公告)号：US20140170822A1

公开(公告)日：2014-06-19

申请号：US14188536

申请日：2014-02-24

Applicant: Micron Technology, Inc.

Inventor： John Zahurak ,  Sanh Dang Tang ,  Gurtej S. Sandhu

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

Abstract translation: 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。