公开(公告)号：US11462289B2

公开(公告)日：2022-10-04

申请号：US17236729

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/419 ,  G11C11/408 ,  G11C11/22 ,  G11C13/00 ,  G11C16/04

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US10998074B2

公开(公告)日：2021-05-04

申请号：US16518824

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C11/408 ,  G11C16/04 ,  G11C29/18 ,  G11C11/419 ,  G11C11/22 ,  G11C13/00

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US20210335436A1

公开(公告)日：2021-10-28

申请号：US17236729

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/419 ,  G11C11/408 ,  G11C11/22 ,  G11C13/00 ,  G11C16/04

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US20210027852A1

公开(公告)日：2021-01-28

申请号：US16518824

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/408 ,  G11C11/419

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US11948651B2

公开(公告)日：2024-04-02

申请号：US17903739

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/22 ,  G11C11/408 ,  G11C11/419 ,  G11C13/00 ,  G11C16/04

CPC classification number: G11C29/18 ,  G11C11/2253 ,  G11C11/2275 ,  G11C11/4085 ,  G11C11/419 ,  G11C13/0028 ,  G11C13/003 ,  G11C16/0483 ,  G11C2029/1804

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.

公开(公告)号：US20230031126A1

公开(公告)日：2023-02-02

申请号：US17903739

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Shane D. Moser

IPC: G11C29/18 ,  G11C11/419 ,  G11C11/408 ,  G11C11/22 ,  G11C13/00 ,  G11C16/04

Abstract: Methods, systems, and devices for word line capacitance balancing are described. A memory device may include a set of memory tiles, where one or more memory tiles may be located at a boundary of the set. Each boundary memory tile may have a word line coupled with a driver and a subarray of memory cells, and may also include a load balancing component (e.g., a capacitive component) coupled with the driver. In some examples, the load balancing component may be coupled with an output line of the driver (such as a word line) or an input of the driver (such as a line providing a source signal). The load balancing component may adapt a load output from the driver to the subarray of memory cells such that the load of the memory tile at the boundary may be similar to the load of other memory tiles not at the boundary.