公开(公告)号：US20200026437A1

公开(公告)日：2020-01-23

申请号：US16038108

申请日：2018-07-17

Applicant: Micron Technology, Inc.

Inventor： Sheng BI ,  Shi Bo ZHANG ,  Yiran LIU ,  Yi Jun LU

IPC: G06F3/06 ,  G06F13/18 ,  G06F13/16

Abstract: A method for managing storage performance consistency, where the method determines a target throughput for writes to a memory sub-system, increases a tracking variable with a granularity based on the target throughput at fixed intervals, decreases the tracking variable based on writes of host data received from a host system to the memory sub-system, and adjusts a priority of host data writes to the memory sub-system relative to writes of reclaimed data from the memory sub-system in response to the tracking variable indicating a deviation from the target throughput.

公开(公告)号：US20200264984A1

公开(公告)日：2020-08-20

申请号：US16559031

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Lyle E. ADAMS ,  Sheng BI ,  Karl D. SCHUH ,  Pushpa SEETAMRAJU ,  Dan Z. TUPY ,  Yongcai XU

IPC: G06F12/1009

Abstract: An entry is read from a first memory component, the entry associated with a first logical address. The first entry includes a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component. The segment of the logical-to-physical address map includes a second entry associated with the first logical address. A second physical address is written to the second entry in the first memory component based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component.