公开(公告)号：US20200264984A1

公开(公告)日：2020-08-20

申请号：US16559031

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Lyle E. ADAMS ,  Sheng BI ,  Karl D. SCHUH ,  Pushpa SEETAMRAJU ,  Dan Z. TUPY ,  Yongcai XU

IPC: G06F12/1009

Abstract: An entry is read from a first memory component, the entry associated with a first logical address. The first entry includes a first physical address to a segment of a logical-to-physical address map in a second memory component and an indication of whether the segment of the logical-to-physical address map is stored in the first memory component. The segment of the logical-to-physical address map includes a second entry associated with the first logical address. A second physical address is written to the second entry in the first memory component based on a determination from the indication that the segment of the logical-to-physical address map is stored in the first memory component.

公开(公告)号：US20220383955A1

公开(公告)日：2022-12-01

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar MUCHHERLA ,  Sampath K. RATNAM ,  Shane NOWELL ,  Sivagnanam PARTHASARATHY ,  Mustafa N. KAYNAK ,  Karl D. SCHUH ,  Peter FEELEY ,  Jiangang WU

IPC: G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.