公开(公告)号：US20200211634A1

公开(公告)日：2020-07-02

申请号：US16818989

申请日：2020-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

公开(公告)号：US11238915B2

公开(公告)日：2022-02-01

申请号：US16818989

申请日：2020-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

公开(公告)号：US10790004B2

公开(公告)日：2020-09-29

申请号：US16218194

申请日：2018-12-12

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C11/406 ,  G11C11/409 ,  G11C11/4091

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.

公开(公告)号：US11315620B2

公开(公告)日：2022-04-26

申请号：US16824460

申请日：2020-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

公开(公告)号：US11270750B2

公开(公告)日：2022-03-08

申请号：US16818989

申请日：2020-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

公开(公告)号：US20220165328A1

公开(公告)日：2022-05-26

申请号：US17650797

申请日：2022-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

公开(公告)号：US11037616B2

公开(公告)日：2021-06-15

申请号：US16220215

申请日：2018-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Shinji Bessho ,  Takuya Nakanishi

IPC: G11C11/40 ,  G11C11/406 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408

Abstract: A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.

公开(公告)号：US20200219556A1

公开(公告)日：2020-07-09

申请号：US16824460

申请日：2020-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

公开(公告)号：US10706909B2

公开(公告)日：2020-07-07

申请号：US16201593

申请日：2018-11-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinji Bessho ,  Toru Ishikawa ,  Takuya Nakanishi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4076

Abstract: A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.

公开(公告)号：US11935576B2

公开(公告)日：2024-03-19

申请号：US17650797

申请日：2022-02-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Ishikawa ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4087

Abstract: An apparatus includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit which is configured to activate first and second internal signals in a time-division manner in response to a first external command A first number of the word lines arc selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal. The second number is smaller than the first number.