公开(公告)号：US20240232008A9

公开(公告)日：2024-07-11

申请号：US18049454

申请日：2022-10-25

Applicant: Micron Technology, Inc.

Inventor： Melissa I. URIBE ,  Aaron P. BOEHM ,  Scott E. SCHAEFER ,  Steffen BUCH

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/102

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

公开(公告)号：US20240061744A1

公开(公告)日：2024-02-22

申请号：US17820120

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Melissa I. URIBE ,  Steffen BUCH

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/079

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

公开(公告)号：US20240419542A1

公开(公告)日：2024-12-19

申请号：US18817713

申请日：2024-08-28

Applicant: Micron Technology, Inc.

Inventor： Melissa I. URIBE ,  Steffen BUCH

IPC: G06F11/10 ,  G06F11/07

Abstract: Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.

公开(公告)号：US20240289035A1

公开(公告)日：2024-08-29

申请号：US18585772

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Gianluca COPPOLA ,  Steffen BUCH

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: In some implementations, a memory device may receive, from a host device, a hardware reset signal. The memory device may determine that a level associated with the hardware reset signal satisfies a threshold for a period of time. The memory device may determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device. The memory device may complete an ongoing memory operation within a remaining time period based on the determination that the host device is expected to power down the memory device.

公开(公告)号：US20240176548A1

公开(公告)日：2024-05-30

申请号：US18511484

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI ,  Steffen BUCH

IPC: G06F3/06 ,  G06F1/30

CPC classification number: G06F3/0659 ,  G06F1/30 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0673

Abstract: Implementations described herein relate to emergency data storing operation selection. In some implementations, a memory device may be configured to receive a peripheral component interconnect power loss notification (PLN) signal and a peripheral component interconnect express reset (PERST) signal. The memory device may be configured to determine whether to initiate a first data storing operation or a second data storing operation based on the PERST signal state based on a falling edge of the PLN signal. The memory device may be configured to selectively initiate the first data storing operation or the second data storing operation. The first data storing operation may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing operation may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss.

公开(公告)号：US20240176507A1

公开(公告)日：2024-05-30

申请号：US18511446

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Steffen BUCH ,  Marco REDAELLI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: Implementations described herein relate to a two-stage emergency data storing operation. In some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. The memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. The first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. The memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.

公开(公告)号：US20240134744A1

公开(公告)日：2024-04-25

申请号：US18049454

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Melissa I. URIBE ,  Aaron P. BOEHM ,  Scott E. SCHAEFER ,  Steffen BUCH

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/102

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.