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公开(公告)号：US11294838B2
公开(公告)日：2022-04-05
申请号：US16942564
申请日：2020-07-29
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna , Jonathan S. Parry
Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.
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公开(公告)号：US20220035758A1
公开(公告)日：2022-02-03
申请号：US16942564
申请日：2020-07-29
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna , Jonathan S. Parry
Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.
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公开(公告)号：US11625299B1
公开(公告)日：2023-04-11
申请号：US17645183
申请日：2021-12-20
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna , Zhengang Chen
IPC: G06F11/10
Abstract: Methods, systems, and devices for inserting temperature information into a codeword are described. A memory system may determine that a predetermined set of bits of a codeword has been received. Based on determining that the predetermine set of bits has been received, the memory system may replace bits of the codeword with temperature information that indicates a temperature of the memory system. The memory system may then store the codeword comprising the temperature information in a memory array.
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Patent Agency Ranking
公开(公告)号：US20220206981A1
公开(公告)日：2022-06-30
申请号：US17573214
申请日：2022-01-11
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna , Jonathan S. Parry
Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.
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公开(公告)号：US11716096B2
公开(公告)日：2023-08-01
申请号：US17735786
申请日：2022-05-03
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna
CPC classification number: H03M13/2906 , G06F11/1004 , G06F11/1068
Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.
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公开(公告)号：US11687477B2
公开(公告)日：2023-06-27
申请号：US17573214
申请日：2022-01-11
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna , Jonathan S. Parry
Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.
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公开(公告)号：US20220337271A1
公开(公告)日：2022-10-20
申请号：US17735786
申请日：2022-05-03
Applicant: Micron Technology, Inc
Inventor： Stephen D. Hanna
Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system may identify, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system may generate one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system may then correct the set of bits based on the candidate set of bits identified as error-free.
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公开(公告)号：US11329673B1
公开(公告)日：2022-05-10
申请号：US17117913
申请日：2020-12-10
Applicant: Micron Technology, Inc.
Inventor： Stephen D. Hanna
Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.
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