Memory device with a clocking mechanism

    公开(公告)号:US10395702B1

    公开(公告)日:2019-08-27

    申请号:US15977125

    申请日:2018-05-11

    Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

    Memory device with a clocking mechanism

    公开(公告)号:US11024349B2

    公开(公告)日:2021-06-01

    申请号:US16401057

    申请日:2019-05-01

    Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

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