公开(公告)号：US09269452B2

公开(公告)日：2016-02-23

申请号：US14331408

申请日：2014-07-15

Applicant: Micron Technology, Inc.

Inventor： Todd Marquart

IPC: G11C16/04 ,  G11C16/34 ,  G11C29/02

CPC classification number: G11C16/349 ,  G11C16/3459 ,  G11C29/028

Abstract: Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract translation: 描述了用于确定系统寿命特性的方法和系统。 许多实施例包括多个存储器设备和耦合到多个存储器设备的控制器。 控制器可以被配置为使用在测试级别上的多个修剪参数对存储器设备的数量执行多个操作，并且至少部分地基于对数量执行的操作的数量来确定系统寿命特性 使用在测试级别的修剪参数数量的存储设备。

公开(公告)号：US09183070B2

公开(公告)日：2015-11-10

申请号：US13949560

申请日：2013-07-24

Applicant: Micron Technology, Inc.

Inventor： Todd Marquart ,  Sampath Ratnam ,  Sean Eilert

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/1048 ,  G06F2212/7204 ,  G06F2212/7206 ,  G06F2212/7211

Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.

Abstract translation: 在一个实施例中，响应于被认为失败的存储器单元的块，休息存储器单元块。 对于一些实施例，可以选择休息块以用于响应于通过操作。 在其他实施例中，可以再次休息一个休息块，或者可以响应于该操作失败而从进一步使用中永久退休。

公开(公告)号：US20210216235A1

公开(公告)日：2021-07-15

申请号：US16744117

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Kevin R. Brandt ,  Todd Marquart

IPC: G06F3/06

Abstract: A first delay value is obtained by a first memory subsystem of a plurality of memory subsystems. The first memory subsystem performs a first scan operation after a first time from a first event for the first memory subsystem. The first time is based on the first delay value. A second memory subsystem of the plurality of memory subsystems performs a second scan operation based upon a second delay value that is different than the first delay value.

公开(公告)号：US20150033087A1

公开(公告)日：2015-01-29

申请号：US13949560

申请日：2013-07-24

Applicant: Micron Technology, Inc.

Inventor： Todd Marquart ,  Sampath Ratnam ,  Sean Eilert

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/1048 ,  G06F2212/7204 ,  G06F2212/7206 ,  G06F2212/7211

Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.

Abstract translation: 在一个实施例中，响应于被认为失败的存储器单元的块，休息存储器单元块。 对于一些实施例，可以选择休息块以用于响应于通过操作。 在其他实施例中，可以再次休息一个休息块，或者可以响应于该操作失败而从进一步使用中永久退休。

公开(公告)号：US20140362647A1

公开(公告)日：2014-12-11

申请号：US14331408

申请日：2014-07-15

Applicant: Micron Technology, Inc.

Inventor： Todd Marquart

IPC: G11C16/34

CPC classification number: G11C16/349 ,  G11C16/3459 ,  G11C29/028

Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.

Abstract translation: 本公开包括用于确定系统寿命特性的方法和系统。 许多实施例包括多个存储器设备和耦合到多个存储器设备的控制器。 控制器可以被配置为使用在测试级别上的多个修剪参数对存储器设备的数量执行多个操作，并且至少部分地基于对数量执行的操作的数量来确定系统寿命特性 使用在测试级别的修剪参数数量的存储设备。

公开(公告)号：US20130083606A1

公开(公告)日：2013-04-04

申请号：US13686487

申请日：2012-11-27

Applicant: Micron Technology, Inc.

Inventor： Todd Marquart

IPC: G11C11/34

CPC classification number: G11C11/34 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/349

Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.

Abstract translation: 本公开包括用于存储器件的寿命标记。 一个或多个实施例包括确定与多个存储器单元相关联的读取干扰值，擦除脉冲量和/或软编程脉冲的量，以及提供读取干扰值的提前和/或退避的指示符 ，擦除脉冲的数量和/或相对于与存储器单元相关联的寿命标记的软编程脉冲的数量。

公开(公告)号：US11650750B2

公开(公告)日：2023-05-16

申请号：US16744117

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Kevin R. Brandt ,  Todd Marquart

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0619 ,  G06F3/0683

Abstract: A first delay value is obtained by a first memory subsystem of a plurality of memory subsystems. The first memory subsystem performs a first scan operation after a first time from a first event for the first memory subsystem. The first time is based on the first delay value. A second memory subsystem of the plurality of memory subsystems performs a second scan operation based upon a second delay value that is different than the first delay value.